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Simultaneous signal packing and pin allocation driven by design

A technology for signal pin and channel assignment, applied in computer-aided design, computing, instrumentation, etc., to solve the problems that software simulation cannot keep up with integrated circuits, lack of scalability, and low efficiency

Pending Publication Date: 2022-04-12
SYNOPSYS INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Conventional software simulation cannot keep up with increasingly complex integrated circuit (IC) products
Hardware-based simulation systems can overcome the inefficiencies and lack of scalability that exist in software-based simulation methods

Method used

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  • Simultaneous signal packing and pin allocation driven by design
  • Simultaneous signal packing and pin allocation driven by design
  • Simultaneous signal packing and pin allocation driven by design

Examples

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Embodiment Construction

[0017] Aspects of the present disclosure relate to simultaneous signal grouping and pin assignments driven by design-under-test (DUT) pin locations.

[0018] Signal communication between a pair of Field Programmable Gate Arrays (FPGAs) is carried through physical devices called sockets. Pinout refers to the assignment of specific design wires to specific sockets. The number of sockets between a pair of FPGAs is limited, which in turn limits the number of signals that can be transmitted between the pair of FPGAs. To overcome this limitation, a technique called Multi-Time Division Multiplexing (MTDMX) can be used, whereby multiple signals share a physical wire. In an exemplary configuration, the multiplexer is deployed in the transmitter side FPGA and the demultiplexer is deployed in the receiver side FPGA, where the signals are sent sequentially at the transmitter side and sequentially at the receiver side take over. Furthermore, different signals are assigned to different M...

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PUM

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Abstract

The embodiment of the invention relates to simultaneous signal grouping and pin allocation driven by pin positions of a design under test. A method includes generating a channel configuration between a first signal pin of a first integrated circuit (IC) die and a second signal pin of a second IC die based on a multiplexed data rate (XDR) of the first signal pin and the second signal pin. The channel configuration includes an association of the XDR to the channel. The method further includes determining a signal pin channel allocation based on the channel configuration; updating a channel configuration based on the signal pin channel allocation and a wire length, the wire length representing a total distance between the first signal pin, the second signal pin and a physical port of the channel; and performing socket instantiation based on the updated channel configuration and the signal pin channel allocation.

Description

[0001] Cross References to Related Applications [0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 084,801, filed September 29, 2020, which is hereby incorporated by reference in its entirety for all purposes. technical field [0003] This disclosure generally relates to design under test. In particular, the present disclosure relates to simultaneous signal grouping and pin assignment driven by pin position of a design under test. Background technique [0004] Conventional software simulation cannot keep up with the increasingly complex integrated circuit (IC) products. Hardware-based simulation systems can overcome the inefficiencies and lack of scalability that exist in software-based simulation methods. A common method for constructing hardware-based simulators is the Multiple FPGA System (MFS). The MFS includes multiple Field Programmable Gate Arrays (FPGAs) with predefined interconnects between each pair of FPGAs. Designs can...

Claims

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Application Information

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IPC IPC(8): G06F30/394G06F30/398
CPCG06F30/347G06F30/392G06F30/394
Inventor 杨宇黄建锋刘时颖
Owner SYNOPSYS INC
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