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Semiconductor storage with auxiliary storage

A storage device and semiconductor technology, applied in static memory, digital memory information, information storage, etc., can solve problems such as difficulty in providing, degradation of memory access efficiency, etc.

Inactive Publication Date: 2004-03-24
SONY CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] In the above-mentioned storage device, only one auxiliary memory 103 is provided, so only one row width data of the memory cell array 102a can be stored, which limits the improvement of data transmission speed, when it is desired to provide a plurality of auxiliary memory to realize high-speed data transmission When, due to the limitation of the design scheme, it is very difficult to provide the same number of auxiliary memory cells as the sense amplifiers, usually, first arrange the column selector, and then configure the registers in accordance with the multiple sense amplifiers
An increase in the number of data transfers and a decrease in the number of transferred bits results in a degradation in memory access efficiency

Method used

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  • Semiconductor storage with auxiliary storage
  • Semiconductor storage with auxiliary storage
  • Semiconductor storage with auxiliary storage

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0023] image 3 The structure of the semiconductor memory device according to the first embodiment of the present invention is shown. exist image 3 Among them, reference numeral 101 represents a read / write buffer (RWBUF), reference numeral 102 represents a memory cell array constituted by DRAM, reference numeral 103a and reference numeral 103b represent auxiliary memories (AUXMEM0, AUXMEM1), and 104a and 104b represent read buffers ( RBUF0, RBUF1). The memory cell array 102 stores data input from an external circuit through the read / write buffer 101 and outputs the stored data to the external circuit through the read / write buffer 101 . In addition, data stored in the memory cell array 102 is transferred to the auxiliary memory 103a via a sense amplifier (not shown).

[0024]The auxiliary memory 103a once stores the data transferred from the sense amplifier, outputs the stored data through the sense buffer 104a, and transfers the stored data to the auxiliary memory 103b. T...

no. 2 example

[0042] Figure 6 The structure of the storage device according to the second embodiment of the present invention is shown. Such as Figure 6 As shown, in the memory device of this embodiment, auxiliary memories 103c and 103d and read buffers 104c and 104d are added to image 3 shown in the first embodiment.

[0043] Differences of this embodiment from the first embodiment are explained below. In response to the transfer control signal S20a, the data stored in the memory cell array 102 is transferred to the auxiliary memory 103a through a transfer gate not shown, and held once in the auxiliary memory 103a. The held data is transferred to the auxiliary memory 103b through an unshown transfer gate in response to the transfer control signal S20b and once held in the auxiliary memory 103b.

[0044] In addition, the data held in the auxiliary memory 103B is transferred to the auxiliary memory 103c through a transfer gate not shown in response to the transfer control signal S20c ...

no. 3 example

[0048] Figure 7The structure of the storage device according to the third embodiment of the present invention is shown. In this embodiment of the memory device, two read buffers 104a0 and 104a1 are connected to the auxiliary buffer 103a, and two read buffers 104b0 and 104b1 are connected to the auxiliary memory 103b.

[0049] The difference between this embodiment and the first embodiment is explained below. In response to the transfer control signal S20a, data stored in the memory cell array 102 is transferred to the auxiliary memory 103a through a transfer gate not shown and held once by the auxiliary memory 103a. Also, in response to the transfer control signal S20b, the data held in the auxiliary memory 103a is transferred to the auxiliary memory 103b through a transfer gate not shown and held once by the auxiliary memory 103b.

[0050] The data held in the auxiliary memory 103a is output in parallel to an external circuit via two read buffers 104a0 and 104a1. Similarl...

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Abstract

A semiconductor memory comprising a memory cell array including a plurality of the memory cells arranged in a matrix, the memory cells being able to be written with and read out data; a reading / writing means for reading and writing data with respect to a selected memory cell; a plurality of auxiliary data storing means arranged in series, a first means among them being connected to the memory cell array and each of the auxiliary data storing means storing a part of the data stored in the memory cell array; a plurality of data output means, each of the data output means being connected to one of the auxiliary data storing means; and a plurality of external data buses, each of the external data buses being connected to one of the data output means; each of the data output means being able to independently output the data stored in a corresponding auxiliary data storing means to a corresponding external data bus.

Description

technical field [0001] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a main memory capable of outputting stored data to an external unit at high speed and consisting of a dynamic random access memory (DRAM). Background technique [0002] In order to improve the efficiency of accessing the storage device, it may be considered to add an additional storage device composed of registers to the DRAM of the main storage device. Once the data stored in the main storage device is transmitted to the auxiliary storage device, the data will be saved. Transfer from the secondary storage device to an external unit. [0003] Such semiconductor memory devices are mainly used for storing image data in computer graphics. In recent years, two-dimensional computer graphics has rapidly evolved into three-dimensional computer graphics, not only in computer-aided design, but also in image generation and video games. ...

Claims

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Application Information

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IPC IPC(8): G11C11/401G06F12/08G11C7/10G11C11/00G11C29/36
CPCG11C7/103G11C11/005G11C29/36G11C11/40
Inventor 谷口一雄宫林正幸山口裕司
Owner SONY CORP