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Semiconductor substrate

A semiconductor and substrate technology, applied in the field of semiconductor substrates, can solve problems such as embrittlement, unfavorable electrical properties, and air gaps on the joint surface

Pending Publication Date: 2022-04-22
ADVANCED SEMICON ENG INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0002] In the post-chip (Chip last) process, the copper pillar (Cu pillar) and the under bump metallurgy (UBM) are mainly used as the connector (interconnector) between the electronic component and the redistribution layer (RDL). The lower melting point bonding medium needs to use solder (solder, such as SnAg) as the bonding material, so after reflow (Reflow), there will be intermetallic compounds (IMC) between Cu and the solder, which is not conducive to electrical properties, although SnAg and Cu A barrier layer (for example, Ni) can be formed between them to limit the diffusion of IMC, but as the size of the bump becomes smaller (for example, below 10 μm), the amount of SnAg must also be reduced, so SnAg and the IMC produced by the Ni layer (Ni 3 sn 4 ) will occupy a large amount of SnAg volume, resulting in air gaps (Void) and embrittlement problems on the subsequent bonding surface

Method used

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  • Semiconductor substrate
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Embodiment Construction

[0026] In order to better understand the spirit of the embodiments of the present application, it will be further described below in conjunction with some preferred embodiments of the present application.

[0027] Embodiments of the present application will be described in detail below. Throughout the specification of the present application, the same or similar components and components having the same or similar functions are denoted by like reference numerals. The embodiments described herein with respect to the accompanying drawings are illustrative, diagrammatic and are used to provide a basic understanding of the application. The examples of the present application should not be construed as limiting the present application.

[0028] As used herein, the terms "approximately," "substantially," "substantially," and "about" are used to describe and account for minor variations. When used in conjunction with an event or circumstance, the terms can refer to instances in whi...

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Abstract

The present invention provides a semiconductor substrate, comprising: an interconnect, the interconnect comprising: a first metal layer on a surface of the semiconductor substrate; the second metal layer is located on the first metal layer; the adhesion layer is located between the first metal layer and the second metal layer, and the adhesion layer is in direct contact with the second metal layer. The invention aims to provide the semiconductor substrate so as to at least improve the yield of the semiconductor substrate.

Description

technical field [0001] Embodiments of the invention relate to semiconductor substrates. Background technique [0002] In the post-chip (Chip last) process, the copper pillar (Cu pillar) and the under bump metallurgy (UBM) are mainly used as the connector (interconnector) between the electronic component and the redistribution layer (RDL). The lower melting point bonding medium needs to use solder (solder, such as SnAg) as the bonding material, so after reflow (Reflow), there will be intermetallic compounds (IMC) between Cu and the solder, which is not conducive to electrical properties, although SnAg and Cu A barrier layer (for example, Ni) can be formed between them to limit the diffusion of IMC, but as the size of the bump becomes smaller (for example, below 10 μm), the amount of SnAg must also be reduced, so SnAg and the IMC produced by the Ni layer (Ni 3 sn 4 ) will occupy a large amount of SnAg volume, resulting in air gaps (Void) and embrittlement problems on the su...

Claims

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Application Information

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IPC IPC(8): H01L21/60
CPCH01L24/12H01L2224/12105H01L2224/81193H01L2224/11
Inventor 陈昭丞张皇贤
Owner ADVANCED SEMICON ENG INC