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Multi-time programmable memory and preparation method thereof

A memory and control area technology, applied in semiconductor devices, electrical solid state devices, electrical components, etc., can solve the problems of large device unit area, low coupling efficiency, low efficiency of programming and erasing, and high energy consumption, and achieve increased contact area large, improve programming and erasing efficiency, and reduce device energy consumption

Active Publication Date: 2022-05-10
晶芯成(北京)科技有限公司 +1
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  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] However, the existing multi-time programmable memory still has the problems of large unit area of ​​the device, high energy consumption, low coupling efficiency, and low programming and erasing efficiency.

Method used

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  • Multi-time programmable memory and preparation method thereof
  • Multi-time programmable memory and preparation method thereof
  • Multi-time programmable memory and preparation method thereof

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Embodiment Construction

[0041] In order to make the purpose, advantages and features of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in very simplified form and not drawn to scale, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention. In addition, the structures shown in the drawings are often a part of the actual structure. In particular, each drawing needs to display different emphases, and sometimes uses different scales. It should also be understood that, unless otherwise specified or pointed out, the terms “first”, “second”, “third” and other descriptions in the specification are only used to distinguish each component, element, step, etc. in the specification, rather than It is used to express the logical relationship or sequence relationship between various compo...

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Abstract

The invention provides a multi-time programmable memory and a preparation method thereof. Part of the gate structure is arranged in the first groove to form the stepped gate structure, so that the contact area of the first well region and the gate structure is increased, the distance of electrons entering the gate structure is shortened, the programming and erasing efficiency of the device is improved, the working voltage is reduced, and the energy consumption of the device is reduced. The gate structure is arranged in the second groove, and part of the gate structure is located in the second groove, so that compared with a planar structure, the contact area of the gate structure arranged in the second groove and the second well region is increased, the coupling efficiency of the capacitor is improved, and the response speed of the device is improved. In addition, due to the arrangement of the first groove and the second groove, the gate structure is of a sunken structure. Under the same device performance, the unit area of the multi-time programmable memory provided by the invention is smaller than the area of a device with the gate structure arranged on a plane.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a multi-time programmable memory and a preparation method thereof. Background technique [0002] With the development of the semiconductor industry and technology, non-volatile memories are widely used in microcontrollers and other fields. In non-volatile memory, by changing the electrical characteristics of the transistors of the device, the magnitude of the current under a certain voltage is different due to the different threshold voltages when writing and erasing. Among them, the multi-time programmable memory (Multi-Time Programmable Memory, MTP) in the non-volatile memory can perform actions such as storing, reading, and erasing data multiple times, and the stored data will not be lost after power off. Disappearance, and its use of a single-layer floating gate structure, can be combined with a normal CMOS process. Therefore, multiple times programmable memory has b...

Claims

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Application Information

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IPC IPC(8): H01L21/28H01L27/11521H01L29/423
CPCH01L29/42356H01L29/4236H01L29/401H10B41/30
Inventor 葛成海李庆民祝进专谢烈翔熊鹏宇
Owner 晶芯成(北京)科技有限公司
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