Packaging method and packaging structure of multi-layer stacked high-broadband memory

Abstract

The invention provides a packaging method and packaging structure of a multilayer stacked high-broadband memory, and the method comprises the steps: respectively providing a substrate and a plurality of groups of memory chips, each group of memory chips comprising a first memory chip and a second memory chip; the first memory chip and the second memory chip are provided with a plurality of conductive through holes; performing hybrid bonding on the first memory chip and the second memory chip to form a plurality of memory micro-modules; sequentially forming a first conductive bump and a second conductive bump on the surface, facing the substrate, of the first memory chip; forming a bonding pad on the surface, deviating from the substrate, of the second memory chip; nesting the second conductive bumps and the bonding pads through a thermocompression bonding process so as to sequentially stack the plurality of memory micro-modules on the substrate in an insulating manner; performing reflow soldering on the plurality of stacked memory micro modules and the substrate through a reflow soldering process; and forming a plastic packaging layer. According to the invention, the stacking of super-multilayer chips can be realized, the production efficiency is improved, and the interconnection of superfine spacing is realized.

Description

technical field [0001] The invention belongs to the technical field of semiconductor packaging, and in particular relates to a packaging method and packaging structure of a multilayer stacked high-bandwidth memory. Background technique [0002] With the development of cloud computing and mobile interconnection, the demand for servers such as data centers has surged. High-end servers require high capacity, large bandwidth, and low power consumption for storage devices. In response to this demand, various companies have successively launched multi-layer stacked storage packaging products based on three-dimensional stacking technology. Such as figure 1 As shown, the multi-layer stacked memory package stack structure uses through-silicon vias 2 to vertically interconnect several memory chips 1, and multiple memory chips 1 are soldered together through bumps 3, and the memory chips 1 are stacked on the substrate 4, and the chips and There is a non-conductive adhesive 5 between...

AI Technical Summary

Problems solved by technology

[0005] At present, the spacing is above 40um. When the spacing is reduced below 25um, due to the small amount of tin, it will be fully converted into an intermetallic compound under heat load conditions, resulting in reliability failure.

[0006] In order to increase storage capacity and data throughput speed, it is necessary to increase the number of chip stacks and the number of pins, but in the current micro-bump mechanism, due to the limitation of bump height and pitch, the space for continuous improvement is limited

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