Manufacturing method of three-dimensional semiconductor structure and three-dimensional semiconductor structure

Abstract

A manufacturing method of a three-dimensional semiconductor structure comprises the steps that a first insulating layer is formed on a lining plate, at least one channel hole is formed in the first insulating layer, and each channel hole penetrates through the first insulating layer and is exposed out of the lining plate; a first epitaxial layer and a second epitaxial layer are sequentially generated in each channel hole in a stacked mode, wherein the first epitaxial layer is a non-uniform doping layer so as to form a source electrode region or a drain electrode region with a low resistance value; forming a second insulating layer and a sacrificial layer which are alternately stacked on the first insulating layer; gradually generating a plurality of first epitaxial layers and a plurality of second epitaxial layers which are alternately stacked on the second epitaxial layer; the invention also provides a three-dimensional semiconductor structure manufactured by the three-dimensional semiconductor structure manufacturing method.

Description

technical field [0001] The invention relates to a manufacturing method of a three-dimensional semiconductor structure and a three-dimensional semiconductor structure prepared by applying the manufacturing method. Background technique [0002] In recent years, in order to meet customer demand for microelectronics with high performance and low manufacturing cost, semiconductor devices need to be highly integrated. The level of integration of a typical two-dimensional or planar semiconductor structure is mainly determined by the area occupied by a unit memory cell, which is affected by the level of technology used to form fine patterns. However, extremely expensive process equipment is required to improve pattern fineness, and thus, the increase in cost limits the development of high integration of two-dimensional or planar semiconductor structures. Therefore, three-dimensional semiconductor structures came into being. Compared with two-dimensional semiconductor structures, t...

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Problems solved by technology

However, the channel holes formed by etching multiple stacked groups are relatively slender, and it is difficult to maintain uprightness and alignment, resulting in skew and offset, so that the related structures of the drain region, source region and gate region of the transistor are prone to be out of alignment. symmetrical or offset

Due to the high resistance of the source region and the drain region of the three-dimensional semiconductor structure, it is difficult to form by ion implantation, and when the three-dimensional semiconductor structure includes a plurality of stacked layers, the source region and the drain region are relatively high. The series resistance value is easy to affect the working current and response speed of the transistor

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