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Method for optimizing layout planning area based on neural network and sequence pair

A floorplanning and neural network technology, applied in neural learning methods, biological neural network models, neural architectures, etc., can solve the problems of opaque training data sets, inability to learn, large search space, etc., to solve the problem of insufficient machine learning data. Effect

Pending Publication Date: 2022-07-05
GUANGDONG UNIV OF TECH
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Problems solved by technology

[0005] Among the above methods, the first method is the idea of ​​​​divide and conquer, that is, the top-level design is divided into many smaller designs until the problem can be solved. This method will lose the quality of the solution and lack the overall view; the second method By looking for the optimal solution in the design space, it is easy to fall into the trouble of local optimal solution, and there is a problem of slow convergence; the third method uses mathematical form to solve the expression composed of module coordinate constraints, and this method can get accurate solution, its complexity increases with the size of the problem, and is limited by the equation expression and the set constraints; the above three methods cannot learn from the experience of the previous iteration
The fourth way is to use the advantages of artificial intelligence in joint optimization to improve the quality of the solution, which is currently a hot spot in the field of floorplanning research, but it has the problems of large search space in each step, high hardware requirements when training the model, and opaque training data sets.

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  • Method for optimizing layout planning area based on neural network and sequence pair
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  • Method for optimizing layout planning area based on neural network and sequence pair

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Embodiment Construction

[0046] For artificial intelligence methods to solve floorplanning, there is the problem of opaque training data sets, which is a common phenomenon in industry and academia. The patent of the present invention will use open source tools to generate datasets and achieve reproducible effects of datasets. In addition, after decades of development, representation-based methods are a type of floorplan representation in floorplanning, which mainly include Polish expressions, B*-trees, O*-trees, sequence pairs, and so on. The representation of sequence pairs is relatively concise and thus becomes the layout representation of the present invention.

[0047] Referring to the accompanying drawings, an optimal method for floorplanning area based on neural network and sequence pair of the present invention includes the following steps:

[0048] Step 1, build a digital integrated circuit floorplanning database with n circuit modules, each piece of data in the database is used to completely...

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Abstract

The invention discloses a layout planning area optimization method based on a neural network and a sequence pair, and the method comprises the steps: firstly constructing a layout planning database through employing a layout planning optimal solution, and solving the problem of insufficient machine learning data size for solving a layout planning problem in integrated circuit electronic design automation; meanwhile, the layout represented by a sequence pair in layout planning is converted into a classification problem in machine learning, finally, a neural network model is built through a multi-layer perceptron, training is conducted, and the trained model is obtained and used for predicting the optimal solution of the layout planning area; according to the method, the optimal scheme of the layout planning area can be quickly and effectively found.

Description

technical field [0001] The invention relates to the field of digital integrated circuit electronic design automation, in particular to a layout planning area optimization method based on a neural network and a sequence pair. Background technique [0002] Inspired by Moore's Law, integrated circuits have entered the era of hyperscale. The number of transistors integrated on a single chip has reached tens of billions, and engineers can no longer manually design circuits to meet the needs of design indicators. In this case, electronic design automation (EDA) technology has emerged, which refers to the design method of using computer-aided design software to complete the functional design, simulation, synthesis, verification, physical design and other processes of very large-scale integrated circuit (VLSI) chips. . Among them, the physical design is the process of converting the circuit information of the netlist into the physical geometric representation, and the final layout...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/392G06F30/27G06K9/62G06N3/04G06N3/08G06F111/06
CPCG06F30/392G06F30/27G06N3/084G06F2111/06G06N3/047G06N3/045G06F18/2415
Inventor 黄益豪蔡述庭邢延熊晓明
Owner GUANGDONG UNIV OF TECH
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