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Wafer level system packaging method and packaging structure

A system packaging and wafer-level technology, applied in the direction of microstructure technology, microstructure devices, manufacturing microstructure devices, etc., can solve the problems of incompatibility with chip technology and low efficiency of wafer-level system packaging, and achieve high packaging efficiency, The effect of saving process steps and simplifying the process

Inactive Publication Date: 2022-07-29
NINGBO SEMICON INT CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The problem solved by the present invention is that the packaging efficiency of the existing wafer-level system packaging is low, and it cannot be compatible with the previous chip formation process, etc.

Method used

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  • Wafer level system packaging method and packaging structure
  • Wafer level system packaging method and packaging structure
  • Wafer level system packaging method and packaging structure

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0034] The present invention provides a wafer-level system packaging method, comprising:

[0035] S01: Provide a device wafer, the surface of the device wafer has a plurality of exposed first bonding pads, a first cavity is formed on the surface of the device wafer, and the first bonding pads are located on the periphery of the first cavity.

[0036] S02: Provide a first chip, where the first chip has a plurality of exposed second pads.

[0037] S03: Bond the first chip to the device wafer, at least part of the first chip is located on the first cavity, the second pad is opposite to the first pad to enclose a first gap, and the first cavity is used as the upper The working chamber of a chip.

[0038] S04: A conductive bump is formed in the first void by an electroplating process, and the conductive bump is electrically connected to the first bonding pad and the second bonding pad.

[0039] It should be noted that S04 in this specification does not represent the order of the ...

Embodiment 2

[0084] refer to Figure 14 , and the difference from Embodiment 1 is that the first chip 3 is formed with a second chip 7 , and the second chip 7 is electrically connected to the first chip 3 . In this embodiment, when the first chip is provided, a plurality of exposed third bonding pads are formed on the first chip 3, and the third bonding pads and the second bonding pads 31 are respectively located on both sides of the first chip 3; After the conductive bumps 5, a second chip 7 is provided; the second chip 7 is then bonded to the first chip 3, and a second gap is formed between the second chip 7 and the first chip 3, and is formed in the second gap The conductive block is used to electrically connect the first chip and the second chip. It should be noted that the second chip 7 may only be electrically connected to the first chip 3 , or may be electrically connected to the device wafer 1 through the first chip 3 .

[0085] The bonding of the second chip 7 and the first chip...

Embodiment 3

[0088] refer to Figure 16 , the first chip 3 in Embodiment 1 is bonded to the front side of the device wafer 1. The difference between Embodiment 3 and Embodiment 1 is that the backside of the device wafer 1 is also bonded to the second chip 7, which is connected to the The device wafer 1 is electrically connected. The method for bonding the second chip 7 to the back of the device wafer 1 includes: providing the second chip 7 , and the second chip 7 is bonded to the back of the device wafer 1 . It should be noted that the bonding and electrical connection method between the second chip 7 and the device wafer 1 refer to the bonding and electrical connection method between the first chip 3 and the device wafer 1 in Embodiment 4, which will not be repeated here. In addition, the second chip 7 may be bonded to the device wafer 1 prior to the first chip 3 , or may be bonded to the device wafer 1 after the first chip 3 is bonded to the device wafer 1 .

[0089] When the second ch...

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Abstract

The invention provides a wafer-level system packaging method and packaging structure, and the method comprises the steps: providing a device wafer, the surface of the device wafer is provided with a plurality of exposed first welding pads, the device wafer is provided with a first cavity, and the first welding pads are located at the periphery of the first cavity; providing a first chip, wherein the first chip is provided with a plurality of exposed second welding pads; the first chip and the device wafer are bonded, at least part of the first chip is located on the first cavity, the second welding pad is opposite to the first welding pad to define a first gap, and the first cavity serves as a working cavity of the first chip on the first cavity; and forming a conductive bump in the first gap through an electroplating process, wherein the conductive bump is electrically connected with the first welding pad and the second welding pad. According to the invention, the conductive bump is formed in the first gap enclosed by the first welding pad and the second welding pad through the electroplating process, so that the first chip is directly and electrically connected with the device wafer.

Description

technical field [0001] The present invention relates to the technical field of semiconductor devices, and in particular, to a wafer-level system packaging method and packaging structure. Background technique [0002] With the development trend of VLSI, the feature size of integrated circuits continues to decrease, and people's requirements for the packaging technology of integrated circuits continue to increase accordingly. Existing packaging technologies include Ball Grid Array (BGA), Chip Scale Package (CSP), Wafer Level Package (WLP), 3D Packaging (3D) and System Package (System Package). in Package, SiP) etc. [0003] At present, in order to meet the goals of lower cost, more reliability, faster and higher density of integrated circuit packaging, advanced packaging methods mainly adopt Wafer Level Package System in Package (WLPSiP). Compared with the traditional system packaging, the wafer-level system packaging is to complete the packaging integration process on the w...

Claims

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Application Information

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IPC IPC(8): H01L21/60H01L21/52H01L23/488B81B7/00B81B7/02B81C1/00B81C3/00
CPCH01L24/81H01L24/82H01L24/11H01L24/83H01L21/52H01L24/32H01L24/16B81C1/00095B81C1/00047B81C1/00261B81B7/0006B81B7/02B81C3/001H01L2224/11462H01L2224/16145H01L2224/32148H01L2224/16225
Inventor 黄河向阳辉刘孟彬
Owner NINGBO SEMICON INT CORP
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