Clock buffer circuit applied to passive voltage mixer
A technology of clock buffer and mixer, applied in the direction of pulse technology, pulse processing, electrical components, etc., can solve the problem of switch nonlinearity, etc., and achieve the effect of improved switch performance, high conversion gain, and high linearity
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[0022] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings.
[0023] The present invention adopts a capacitive voltage dividing mode clock buffer (ie: dual-gate cascode), which can achieve high output swing and small upper and lower edge delays. As a high-speed clock amplifier, it can The protection transistor is in a safe zone, extending the life of the transistor.
[0024] The dual-gate layout can improve the speed of the buffer and improve the driving capability of the subsequent stage. The cascode can protect the switch in the safe area and prolong the life of the device.
[0025] figure 1 The circuit diagram of the clock buffer in the form of dual-gate cascode.
[0026] Input terminals of the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 are electrically connected to provide input signals.
[0027] The gate of the first transistor M1 is electrical...
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