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Clock buffer circuit applied to passive voltage mixer

A technology of clock buffer and mixer, applied in the direction of pulse technology, pulse processing, electrical components, etc., can solve the problem of switch nonlinearity, etc., and achieve the effect of improved switch performance, high conversion gain, and high linearity

Active Publication Date: 2022-07-29
奉加微电子(昆山)有限公司 +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to provide a clock buffer and its circuit applied to a passive passive voltage mixer, which can improve the clock swing or introduce a high-speed bootstrap circuit to solve the problem of switch nonlinearity

Method used

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  • Clock buffer circuit applied to passive voltage mixer
  • Clock buffer circuit applied to passive voltage mixer
  • Clock buffer circuit applied to passive voltage mixer

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Embodiment Construction

[0022] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings.

[0023] The present invention adopts a capacitive voltage dividing mode clock buffer (ie: dual-gate cascode), which can achieve high output swing and small upper and lower edge delays. As a high-speed clock amplifier, it can The protection transistor is in a safe zone, extending the life of the transistor.

[0024] The dual-gate layout can improve the speed of the buffer and improve the driving capability of the subsequent stage. The cascode can protect the switch in the safe area and prolong the life of the device.

[0025] figure 1 The circuit diagram of the clock buffer in the form of dual-gate cascode.

[0026] Input terminals of the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 are electrically connected to provide input signals.

[0027] The gate of the first transistor M1 is electrical...

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Abstract

The invention belongs to a passive frequency mixer in a wireless transceiver, and particularly relates to a circuit of a clock buffer applied to a passive voltage frequency mixer, a third capacitor C3, a fifth capacitor C5, a second capacitor C2 and a sixth capacitor C6 are used as capacitive voltage dividers to perform signal voltage dividing processing, and the clock buffer is applied to the passive voltage frequency mixer. And the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 are in a good working interval in cooperation with the first voltage bias VB1, the second voltage bias VB2, the third voltage bias VB3 and the fourth voltage bias VB4. The first transistor M1 and the second transistor M2 or the third transistor M3 and the fourth transistor M4 form a double-gate and common-source and common-gate mode, so that the second transistor M2 protects the first transistor M1, and the third transistor M3 protects the fourth transistor M4. On the premise of reliability and safety, the oscillation amplitude of the clock is reasonably improved, so that the switching performance of the mixer is further improved.

Description

technical field [0001] The invention belongs to a passive passive mixer in a wireless transceiver, in particular to a circuit applied to a clock buffer of a passive passive voltage mixer. Background technique [0002] The current era is an era of rapid development and an era of information explosion. It is difficult to meet people's increasing data needs by relying on traditional transceivers. Therefore, broadband high-speed radio frequency transceivers came into being. It can be said that it is an era of development. inevitable product. However, broadband, high linearity, low noise, and high speed, each of these indicators are trade-offs for hardware IC implementation, and it is difficult to comprehensively improve these indicators. Therefore, designers are currently looking for solutions to comprehensively improve these indicators, and therefore have been promoting the development of integrated circuits. [0003] With the requirements of broadband, high speed and high po...

Claims

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Application Information

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IPC IPC(8): H03K5/134H03D7/14
CPCH03K5/134H03D7/1466
Inventor 蒋明澔
Owner 奉加微电子(昆山)有限公司