Clock correction method, clock data recovery circuit, chip, receiving end and terminal

Abstract

The invention discloses a clock correction method, a clock data recovery circuit, a chip, a receiving end and a terminal. The method comprises the following steps: acquiring at least two clock signals with the same frequency output by a phase interpolator; wherein the phase interpolator is configured to maintain a first phase relationship between the at least two clock signals; acquiring a phase control code of the phase interpolator when a second phase relationship is formed between the at least two clock signals and a data signal; calculating a phase control code deviation value based on a first phase control code difference value between the phase control codes of the at least two clock signals and a second phase control code difference value corresponding to the first phase relationship; and generating a target phase control code according to the phase control code deviation value, wherein the target phase control code is used for configuring the phase interpolator to correct the first phase relation. According to the scheme of the embodiment of the invention, high accuracy of data recovery of the CDR circuit is realized, the occupied circuit area is small, and the precision is high.

Description

technical field [0001] One or more embodiments of this specification relate to the technical field of circuit manufacturing, and in particular, to a clock correction method, a clock data recovery circuit, a chip, a receiving end, and a terminal. Background technique [0002] The clock data recovery circuit (Clock Data Recovery CDR) is widely used in various high-speed serial communication scenarios, such as optical communication, board-level, chip-level high-speed signal transmission and so on. Its purpose is to recover the clock signal synchronized with the received data signal. [0003] Common types of clock data recovery circuits (CDR) are, for example, based on phase locked loop (PLL), delay locked loop (DLL) or phase interpolator (PI) implementations. like figure 1 As shown, taking the four-phase half-speed sampling CDR based on PI as an example, the four-way clock signals clk_i, clk_q, clk_ib, clk_qb are used to sample and restore the input data, and the clock freque...

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Problems solved by technology

[0008] However, this method requires an analog circuit to implement the above-mentioned relatively complex logic calculation, which will occupy a large circuit area and power consumption

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