Method for producing semiconductor device
A semiconductor and device technology, applied in the field of manufacturing semiconductor devices
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[0022] Two configurations of memory cells known per se are explained with the aid of FIG. 1 to which the method according to the invention can be applied in each case. What is common to both configurations is that the switching transistors S1, S2 in the lower plane are formed directly on the semiconductor substrate 1, and the storage capacitors K1, K2 are arranged in the upper plane, the two planes being connected via the The insulating layers 4 therebetween are separated from each other.
[0023] According to a first configuration ("stacked cell"), the switching transistor S1 and the storage capacitor K1 are mainly arranged directly on top of each other, the lower electrode 31 of the storage capacitor S1 being a contact hole filled with an electrically conductive material. 41 ("plug") is electrically connected to the drain region 21 of the MOS transistor S1,2 through the insulating layer 4.
[0024] According to the second construction scheme ("bias unit (offset cell)"), the...
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