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Method for improving reliability of non-volatile memory cell and structure thereof

A non-volatile storage and reliability technology, applied in the manufacturing of electrical components, electric solid state devices, semiconductor/solid state devices, etc., can solve the problems of reducing product reliability and charge loss, and achieve the effect of improving the reliability of components

Inactive Publication Date: 2005-06-29
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0014] However, the above-mentioned free ions (mobile ions) will still penetrate the silicon oxide spacer (spacer) 130 and get close to the gate structure 120, so that the charge stored in the floating gate 124 will be lost and the reliability of the product will be reduced. (reliability)

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  • Method for improving reliability of non-volatile memory cell and structure thereof
  • Method for improving reliability of non-volatile memory cell and structure thereof
  • Method for improving reliability of non-volatile memory cell and structure thereof

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Embodiment Construction

[0035] Please refer to Figure 2-7 . figure 2 --7 shows a sectional view of the manufacturing method according to the present invention. First, please refer to figure 2 , providing a semiconductor substrate 200, wherein the substrate 200 has at least one gate structure 210 of any possible non-volatile memory, such as erasable and programmable read-only memory (erasable programmable read-only memory; EPROM), electrically erasable and programmable read-only memory (electrically erasable programmable read-only memory; EEPROM) or flash memory (flash memory)...etc. In this embodiment, a flash memory is taken as an example. Wherein the forming method of the gate structure 210 first forms, for example, SiO 2 A tunnel oxide layer 211 of the layer is on part of the substrate 200; then a floating gate 212 such as a polysilicon layer is formed on the tunnel oxide layer 211; and then formed such as SiO 2 An inter-gate dielectric layer 213 of ONO layer or ONO layer is formed on the ...

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Abstract

The present invention relates to a method and its structure for improving the reliability of a non-volatile memory unit. The method is to sequentially form a pad oxide layer spacer with a thickness of about 100 angstroms on the side wall of the gate structure of the memory unit, a thickness of A nitride spacer with a thickness of about 200 angstroms, and an oxide spacer with a thickness of about 2000 angstroms. In this way, since the nitride layer spacer can reduce free ions (mobileions) approaching the memory cell, the charge stored in the memory cell will not be lost, thereby improving the reliability of the device.

Description

technical field [0001] The present invention relates to a semiconductor manufacturing method and structure, in particular to a method and structure for improving the reliability of a non-volatile memory unit, that is, a manufacturing method and structure for reducing the loss of stored charge in a non-volatile memory unit . Background technique [0002] Memory can be divided into two categories: volatile memory and non-volatile memory. Among them, non-volatile memory is characterized by its memory function, that is, even after the power is turned off, the non-volatile memory The stored data can still be preserved, such as: Mask ROM (maskROM), One Time Programmable ROM (OTP ROM), Erasable and Programmable ROM (EPROM), Electrically Erasable and Programmable Read-only memory (EEPROM), memory (flashmemory), multiple times programmable read-only memory (MTP ROM), etc. [0003] In the traditional manufacturing process, borophosphosilicate glass (BPSG) is often used as the inter-...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H10B20/00H10B99/00
Inventor 曾铕寪邱宏裕吕文彬黄宝玲
Owner MACRONIX INT CO LTD