Electronic packaged component with high density interconnection layer
A technology for electronic devices and multilayer interconnection, which is applied in the field of organic multilayer interconnection structures, can solve problems such as easy damage, failure, and rupture, and achieve the effect of avoiding process steps
Inactive Publication Date: 2005-08-03
ULTRATECH INT INC
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Problems solved by technology
If the redistribution layer cannot accommodate thermal stress, the surface redistribution layer is susceptible to damage, such as cracking, which can cause failure of the interconnection between the organic chip carrier and the semiconductor chip, and between the organic chip carrier and the printed circuit board
Method used
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Embodiment Construction
[0033] The present invention provides an electronic package comprising a multilayer interconnect structure (such as a substrate comprising an organic dielectric material such as an organic chip carrier) and a semiconductor chip, the multilayer interconnect structure being relatively compliant and having about A coefficient of thermal expansion (CTE) of 10-12 ppm / °C does not cause failure of the interconnection between the semiconductor chip and the printed circuit board capable of mounting the package. As in embodiments of the present invention, the multilayer interconnection structure may consist of a single layer. Failure of an interconnect, such as a solder interconnect, is defined as an increase in the resistance of the interconnect of at least 1 ohm as a result of being subjected to each test (i.e., test level) of the Thermal Acceptance Test (TAT), where at each TAT test , the interconnection is actually tested, or subjected to engineering calculations or computer simulat...
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Abstract
A method of making a multi-layered interconnect structure. First and second electrically conductive members are formed on the first and second dielectric layers, respectively. The dielectric layer are formed on opposing surfaces of a thermally conductive layer. A first and second electrically conductive layer is formed within the first dielectric layer. The second electrically conductive layer includes shielded signal conductors and is positioned between the first electrically conductive layer and the thermally conductive layer. A plated through hole (PTH) formed through the interconnect structure is electrically connected to one of the first and second electrically conductive members and to one of the shielded signal conductors. A third dielectric layer, formed on the first dielectric layer and on portions of the first electrically conductive members, substantially overlies the PTH and includes a high density interconnect layer for providing an electrical path from an electronic device to the shielded signal conductors.
Description
[0001] This patent application is a continuation-in-part of co-pending US Patent Application SN: 09 / 346,356, filed July 2, 1999, and entitled "Electronic Packages for Electronic Components and Methods of Making Same." technical field [0002] The present invention relates generally to electronic packages for interconnecting semiconductor chips to printed circuit boards, and more particularly to organic multilayer interconnect structures including high density interconnect layers such as allylated surface layers. Background technique [0003] Organic substrates such as chip carriers have been and continue to be developed for many applications. Organic substrates are expected to replace ceramic substrates in many chip carrier applications due to their low cost and good electrical properties. Organic substrates, such as organic chip carriers used in electronic packages to interconnect semiconductor chips to printed circuit boards, can have surface redistribution layers to redis...
Claims
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IPC IPC(8): H01L23/32H01L21/48H01L23/373H01L23/498H05K1/11H05K3/42H05K3/46
CPCH05K3/4626H05K2201/10378H01L2924/01046H05K3/4641H01L21/4853H01L2924/01004H05K2201/09509H01L2924/01019H01L2924/01322H01L2924/15311H05K3/4602H05K2201/0141H01L23/49822H05K2201/09536H05K2201/09554H01L23/3735H05K3/4608H01L2924/3011H05K1/114H05K2201/0191H01L2924/01068H05K3/4688H05K3/429H05K2201/0959H05K2201/068H01L2924/01078H05K3/4632H05K3/4623H01L2224/16225H01L2924/3025H01L2924/12044H05K2201/096H01L2924/00014Y10T29/49155Y10T29/49165H01L2224/0401
Inventor 小弗朗西斯·J·唐斯唐纳德·S·法夸尔伊丽莎白·福斯特罗伯特·M·雅皮杰拉尔德·W·琼斯约翰·S·克雷斯吉罗伯特·D·塞贝斯塔戴维·B·斯通詹姆斯·R·威尔科克斯
Owner ULTRATECH INT INC