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Method for manufacturing imbedded non-volatile memory with sacrificed layer

A manufacturing method and gate dielectric layer technology, which can be used in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., and can solve problems such as inability to effectively shorten transistor channels.

Inactive Publication Date: 2006-12-20
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, today's oxidation and high-temperature heat flow injection of dopants (dopants) can not effectively shorten the channel of the transistor when it diffuses. This phenomenon is called thermally enhanced diffusion and oxidation enhanced diffusion.

Method used

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  • Method for manufacturing imbedded non-volatile memory with sacrificed layer
  • Method for manufacturing imbedded non-volatile memory with sacrificed layer
  • Method for manufacturing imbedded non-volatile memory with sacrificed layer

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Embodiment Construction

[0057] The detailed manufacturing method and practical application disclosed in the present invention will be described as follows with reference to the accompanying drawings. Figure 1A ~ Figure 1B It is a flowchart of a manufacturing method drawn according to an embodiment of the present invention. Figure 2 to Figure 10 Illustrated structure diagram of Figure 1A ~ Figure 1B related steps. and Figure 11 It is a sectional view of an embedded non-volatile memory structure with a SONOS memory unit drawn by applying the present invention.

[0058] Please refer to Figure 1A ~ Figure 1B , each step will be described in numerical order from step block 10 to step block 23 to illustrate the manufacturing method of the present invention. First, as described in step block 10 , an array area 110 and a non-array area 111 are defined on the substrate 100 by separating the substrate 100 with a dielectric region 112 . As shown in FIG. 2, the dielectric region 112 is formed on the subst...

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Abstract

The invention discloses a method for preparing non-volatile memory in high density such as mask ROM or SONOS memory. The said non-volatile memory and advanced peripheral logic modules are integrated on single chip. The method includes steps: covering gate dielectric layer by a sacrificial layer of silicon nitride; in implantation step, using mask to define pattern of line structure on sacrificial layer of silicon nitride; depositing a dielectric material to fill in gaps in line structure; flattening step to remove sacrificial layer of silicon nitride, and a polycrystalline silicon layer is covered; defining word line in array zone, and defining gate structure of transistor in non array zone; and steps of using low doping drain (LDD), silicide and other logic circuits.

Description

technical field [0001] The invention relates to a manufacturing method of a non-volatile memory with a small key size, in particular to a manufacturing method suitable for an embedded memory on a complex integrated circuit. Background technique [0002] With the development of integrated circuit manufacturing technology, the size of components on the integrated circuit is gradually reduced, and the degree of integration of functional blocks on a single chip is also gradually increased. Therefore, many embedded non-volatile memory chips containing logic functional components have been designed, such as memory controllers, general-purpose processors, input / output interface logic, dedicated Logic (dedicated logic), digital signal processors (digital signal processors) and various chips with other functional units. [0003] At present, there are still some problems to be solved in the design and manufacture of small-sized complex integrated circuits. For example, the smaller t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8234H01L21/8239H10B99/00
Inventor 黄仲仁
Owner MACRONIX INT CO LTD
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