Use of CsOH in dielectric CMP slurry

A dielectric layer and integrated circuit technology, applied in the direction of circuits, electrical components, polishing compositions containing abrasives, etc., can solve the problems of high polishing defect rate, poor planarization effect, and low polishing rate

Inactive Publication Date: 2002-12-25
CABOT MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, ammonia has a strong odor
In addition, the slurry planarization effect is poor compared to potassium slurry, the degree of polishing defect rate is high and the polishing rate is low

Method used

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  • Use of CsOH in dielectric CMP slurry
  • Use of CsOH in dielectric CMP slurry
  • Use of CsOH in dielectric CMP slurry

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0044] This example evaluates the ability of compositions containing various oxyhydroxides to polish silicon-containing substrates with high efficiency and low defectivity.

[0045] The polishing slurry compositions are shown in Table 1 below. Each polishing composition contains CAB-O-SPERSE manufactured by Cabot Corporation  SC-E calcined silica. The slurries were stabilized with CsOH or KOH, ie each base was added to each slurry in sufficient amount to increase the slurry pH to 10.8. The polishing composition was used to planarize a test wafer. The test wafer is a test pattern of a mask designed for MIT, in which aluminum lines are grown on a silicon substrate. The wafer has a step height of approximately 9000 Angstroms. The pattern has a line pitch of 250 microns with a regularly varying density ranging from 100 to 8%, where 100% means 100% of the overlay area and 25% means the lines are thick enough that 25% is overlay area and 75% is field area.

[0046] Field meas...

Embodiment 2

[0058] In the present embodiment, it is to evaluate including CsOH, KOH and NH 4 Planarization rate of OH polishing slurries. Each of the tested slurries contained 12 weight percent CAB-O-SPERSE  SC-E calcined silica (manufactured by Cabot Corporation). The slurry is made of CsOH, KOH or NH 4OH stabilization, ie sufficient amount of each base was added to each slurry to increase the slurry pH to 10.8. Each of the slurries was used to polish the wafers described in Example 1 according to the method described in Example 1.

[0059] Flatten the result with Figure 5 and Figure 6 Illustrated. according to Figure 5 , the planarization rates of CsOH and KOH slurries are better than those containing NH 4 OH slurry. according to Figure 6 , the slurry containing CsOH is more than that containing KOH or NH 4 OH slurries also planarize silicon substrates more efficiently. with KOH and NH 4 Compared with the OH slurry, the CsOH slurry can be seen to have greater efficienc...

Embodiment 3

[0061] This example evaluates the planarization rate of commercially available polishing slurries. The first slurry, D7000, is a 10.5 weight percent dispersion of fumed silicon stabilized with KOH. The second slurry was Klebsol 30N50, a colloidal silica (manufactured by Clariant) stabilized with 30 weight percent ammonia. Each of the slurries was used to polish the wafers described in Example 1 according to the polishing method described in Example 1.

[0062] The planarization results are shown in Table 2.

[0063] Serum Composition

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PUM

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Abstract

Chemical mechanical polishing compositions including an abrasive and cesium hydroxide and methods for polishing dielectric layers associated with integrated circuits using cesium hydroxide containing polishing compositions.

Description

technical field [0001] The present invention relates to chemical mechanical polishing compositions comprising an abrasive and cesium hydroxide. The present invention also relates to methods of polishing dielectric layers incorporated into integrated circuits using a cesium hydroxide-containing polishing composition. Background technique [0002] An integrated circuit is composed of millions of active components formed on or in a silicon substrate. The active components, initially separate from each other, are interconnected to form functional circuits and components. The components are connected to each other by using multi-stage connections. The interconnect structure typically has a first metallization, a connection layer, a second level of metallization and sometimes a third and subsequent level of metallization. Different levels of metallization in silicon substrates or wells are achieved using interlevel dielectrics (ILDs) such as doped and undoped silicon dioxide (S...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): B24B57/02C09G1/02C09K3/14H01L21/304H01L21/306H01L21/3105
CPCC09K3/1463H01L21/31053H01L21/302
Inventor 艾丽西亚·F·沃尔特斯布赖恩·L·米勒詹姆斯·A·德克森保罗·M·菲尼
Owner CABOT MICROELECTRONICS CORP
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