Semiconductor storage device

Abstract

A semiconductor storage device operating according to SRAM specifications in which normal access is not delayed by the effect of refresh and the memory cycle can be shortened as compared with conventional one. An ATD circuit (4) is subjected to variation of address (Address) and generates a one-shot pulse in an address variation detection signal (ATD) after an address skew period. In response to a write request, a write enable signal ( / WE) is caused to fall during the address skew period. Write or read is started at the rise of the one-shot pulse. When write is performed, late write is performed, using an address and data provided when write is requested immediately before. Subsequently, refresh is performed within a period from the fall of the one-shot pulse and to the end of the address skew period of the next memory cycle. For the late write performed in response to the next write request, an address and data are taken into register circuits (3, 12) at the rise of the write enable signal ( / WE).

Description

field of invention [0001] The present invention relates to a semiconductor memory device. The memory cell array is composed of the same memory cells as DRAM (Dynamic Random Access Memory), and when viewed from the outside of the semiconductor memory device, its operating specifications are the same as those of general-purpose SRAM (Static RAM). same. In particular, the present invention relates to a standby semiconductor storage device suitable for portable devices such as portable phones and PHS (Personal Handyphone System). Background technique [0002] As semiconductor devices capable of random access, the most representative ones are SRAM and DRAM. Compared with DRAM, SRAM is generally faster. As long as the power is supplied and the address is input, the change of the address can be captured, and the internal sequential logic circuit is activated to perform reading and writing. In this way, compared with DRAM, SRAM can operate only by providing a simple input signal w...

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Problems solved by technology

[0029] In view of the foregoing, an object of the present invention is to provide a semiconductor memory device that does not slow down normal read / write access due to the influence of the update, and does not cause access delay even when there is a skew phenomenon in the address. In order to solve problems such as damage to the memory cell, by reducing the writing time, the overall time of the memory cell can be shortened, and even when the general-purpose SRAM standard is operated and the capacity is increased, the chip size is small, the power consumption is low, and an inexpensive semiconductor is provided. storage device

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