Semiconductor device and its production method

Abstract

The present invention relates to a semiconductor device and its making method. Its making method includes the following steps: firstly, electrically connecting electronic element on first base plate,then connecting said first base plate on semiconductor chip or second base plate, after the semiconductor chip is connected on the second base plate, electrically connecting first base plate, second base plate and chip, then making the above-mentioned material undergo the processes of die-pressing, sphere-planting and cutting so as to can obtain the invented product.

Description

technical field [0001] The present invention relates to a semiconductor device and its manufacturing method, especially to a semiconductor device integrated with electronic components such as passive components and its manufacturing method. Background technique [0002] In order to improve the performance of a general semiconductor device, electronic components such as passive components are often added to the semiconductor device. For example, U.S. Patents No. 5,264,730, No. 5,311,405, No. 5,811,880, No. 5,825,628, and No. 6,316,828, etc., disclose that passive components are arranged on the substrate of a ball grid array (BGA) package to improve packaging The technical content of the overall electrical function of the component. [0003] The substrate configuration of such a semiconductor device with passive components such as Figure 9 Preferably, passive components 40 such as resistors or capacitors are connected to the ground ring (Ground Ring) 13 and power ring (Power...

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Problems solved by technology

[0004] However, due to the addition of passive components 40 in this configuration of the substrate 10, the layout gap P of the bonding pad (Bond Finger) 11 between the passive components 40 will be forced to be narrowed from the traditional 0.150 mm to a small The gap (Fine Pitch) of 0.125mm causes a substantial increase in manufacturing costs

[0005] In addition, the arrangement of the above-mentioned passive components 40 will also cause the wiring of the substrate 10 to avoid the passive components 40 so that the wiring area and space are limited, thereby affecting the overall design of the substrate; wiring, the number and location of passive components 40 are also limited, resulting in a bottleneck in the performance improvement of semiconductor devices

[0006] Furthermore, if the passive element 40 must be placed near the periphery of the chip 20 other than the corner in order to meet the actual needs, it is often because the wire 30 bypasses the passive element 40 by the bonding pad (Bond Pad) 21 of the chip 20 and electrically connected to the corresponding bonding wire pad 11 of the substrate 10, so that it is easy to occur such as Figure 10 The wire 30 shown touches the corner edge of the passive component 40 and causes a short circuit, which further affects the yield rate of the wire bonding and the reliability of the product

Although this shortcoming of easy short circuit can be solved by coating the passive element 40 with a layer of insulating material in advance, such an increase in the process will also bring about a substantial increase in production costs.

[0007] In order to solve the above problems, although U.S. Patent No. 5,670,824 provides a structure in which passive components are integrated on a board and placed under the chip, this integrated passive component board cannot use traditional Passive components such as resistors or capacitors are very expensive, so it is difficult to meet market demand and cannot be mass-produced

[0008] In addition, although China Taiwan Patent Application No. 89121891 also proposes that Figure 11 The shown structure directly electrically connects the passive element 40 to the chip 40, but this kind of structure must form the bonding pad 22 of the passive component 40 on the chip 20 in advance, and perform soldering on the bonding pad 22. The Under Bumping Metalization process (Under Bumping Metalization) is used to electrically connect with the solder paste (Solder Paste) of the passive component 40, which leads to a complicated process and a significant increase in manufacturing cost

[0009] The patent also proposes a Figure 12 As shown, the passive component 40 is directly glued on the chip 20, and then the passive component 40 is electrically connected to the power ring 12 and the ground ring 13 on the substrate 10 by wires 42 and 43 respectively. The contact terminal (Terminal) of the passive component 40 of the structure is not smooth enough, so it is difficult to use the wire bonding machine of the traditional packaging process to perform wire bonding.

Therefore, this structure cannot meet the market demand because it is difficult to carry out mass production under the existing equipment and process framework.

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