Method for mfg. selective local self-aligned silicide

Abstract

A process for preparing the selectively local self-alignment silicide includes covering a common barrier layer on the memory unit region with more narrow gaps, generating another barrier layer on substrate to cover the memory unit region and logic circuit region, and back etchnig to expose the polysilicon gate and silicon substrate, where said self-alignment silicide is formed, and selectively generating the local self-alignment silicide.

Description

technical field [0001] The present invention relates to a method for fabricating a self-aligned silicide (Salicide for short), and in particular to a method for fabricating a selective (Partial) self-aligned silicide. Background technique [0002] In deep sub-micron integrated circuit technology, due to the gradual reduction of line width, contact area and junction depth, in order to effectively improve the working quality of components, reduce resistance and reduce signal transmission caused by resistance and capacitance Delay (RC Delay), so when making the gate, a layer of metal silicide (Silicide) is formed on the polycrystalline gate. [0003] Since lithography is not required in the metal silicide process, the metal silicide produced by this type of process is also called self-aligned metal silicide. Figure 1A to Figure 1C is a cross-sectional view of a known selective localized self-aligned silicide fabrication process. [0004] Please refer to Figure 1A On the sub...

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Problems solved by technology

Since the self-aligned silicide 114 is easily formed on the substrate 100 of the memory cell region 102, the process margin is greatly reduced, and the diffic

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