Field effect transistor adapted for extra-dup submicrometer field and preparation process thereof

Abstract

A fieldistor includes a source-drain, grating medium, grating electrode, channel and a substrate in which, a first medium isolation layer is vortical to the channel direction between the source-drainand the substrate, a connection part of the source-drain and the channel is between top of the first medium isolation layer and the channel surface, a second medium isolation layer parallel to the channel and between the source-drain bottom and substrate is formed to a L shape with the first. Optional extending technology is applied to prepare the first medium layer then to inject combined HHe toprepare the second medium isolation layer, controlling short channel effect.

Description

technical field [0001] The invention belongs to the technical field of the structure of a field effect transistor (Metal-Oxide-Silicon Field Effect Transistor) in a CMOS ultra-large-scale integrated circuit (ULSI) and its manufacturing method, especially the field effect transistor structure and its method of manufacture. Background technique [0002] With the CMOS VLSI technology entering the sub-0.1 micron field, the field effect transistors in the circuit have serious short channel effects, which is manifested by the decrease of the threshold voltage (threshold voltage) as the channel length decreases. The threshold voltage decreases as the drain terminal voltage increases, and the source-drain direct punch-through or off-state drain leakage current increases. The short channel effect will cause the field effect transistor to completely or partially fail to work, thereby causing circuit failure. Therefore, controlling the short channel effect is the most important subje...

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Problems solved by technology

[0008] None of the above methods can achieve a good trade-off be

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