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Semiconductor storing device with subamplifier

A storage device and semiconductor technology, applied in semiconductor/solid-state device manufacturing, information storage, static memory, etc., can solve problems such as increasing circuit area, and achieve the effect of preventing data amplitude from becoming smaller

Inactive Publication Date: 2004-08-04
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, in the conventional semiconductor memory device, an additional circuit area is required in the precharge circuit portion, and as a result, there is a problem that the circuit area of ​​the entire semiconductor memory device increases.

Method used

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  • Semiconductor storing device with subamplifier
  • Semiconductor storing device with subamplifier
  • Semiconductor storing device with subamplifier

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0029] FIG. 2 is a circuit diagram showing the circuit configuration of the cross belt 6 and its periphery in the first embodiment.

[0030] As shown in FIG. 2, the sense amplifier band 3 of the peripheral circuit includes: a sense amplifier 10; bit line separation control circuits 20L, 20R; bit line equalizers 30L, 30R; and N-channel MOS transistors 41, 42. The crossband 6 is provided with: a sense amplifier activation circuit 50 , an input / output conversion circuit 60 , an LIO line equalizer 70 , a VBL precharge circuit 80 and a sub-amplifier 100 .

[0031] First, the circuit configuration in the sense amplifier band 3 will be described in detail.

[0032] Sense amplifier 10 is connected between the pair of bit lines BLO, / BLO, and includes N-channel MOS transistors 11, 12 and P-channel MOS transistors 13, 14. Sense amplifier 10 amplifies a slight voltage difference read from a bit line pair BLO, / BLO of a memory cell (not shown) by a potential supplied via sense amplifier ...

Embodiment 2

[0062] The sub-amplifier 100 in Embodiment 1 adopts the structure and configuration to amplify the small voltage difference of the LIO line pair.

[0063] However, when the overall parasitic resistance of the hierarchical input and output lines in the memory cell array, the wiring resistance of the GIO line pair, and the capacitance of the capacitor play a dominant role, for example, at the time of reading, the data read from the sense amplifier 10 is displayed on the LIO line pair. The resulting voltage difference becomes large enough in a short time, but it takes a long time to generate a sufficient voltage difference on the GIO line pair used for transmission. In this case, the sub-amplifier 100 is effective in preventing the reduction of the amplitude of the data read in the read / write control circuit 5 via the gradation input / output line from being weakened.

[0064] In addition, since the sub-amplifier is activated only during the read operation, it is important how the ...

Embodiment 3

[0072] FIG. 8 is a circuit diagram showing the circuit configuration of the cross belt 6 and its periphery according to the third embodiment.

[0073] The difference between the circuit structure of the cross belt 6 and its surroundings in Embodiment 3 shown in FIG. 8 and the circuit structure of the cross belt 6 and its surroundings in Embodiment 2 shown in FIG. 6 lies in that the sub amplifier 100A and the input The output conversion circuit 60 is replaced with a sub-amplifier+input-output conversion circuit 200 that integrates both functions. The specific circuit structure of the sub-amplifier+input-output conversion circuit 200 is as follows.

[0074] Figure 9 It is a circuit diagram showing a specific circuit configuration of the sub-amplifier+input-output conversion circuit 200 of the third embodiment.

[0075] Figure 9 The sub-amplifier+input-output conversion circuit 200 of the third embodiment shown includes the same sub-amplifier 100A and input-output conversion...

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PUM

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Abstract

By connecting a sense amplifier driving line (S2N) to a source of an N-channel MOS transistor (103), voltages (Vgs) between gates and sources of N-channel MOS transistors (101, 102) become 0 volt since the sense amplifier driving line (S2N) and a couple of (LIO) lines are both on the precharge potential (VBL) even though a control signal (LAMPE) temporarily becomes H level, then a sub-amplifier (100) does not operate. Consequently, the addition of a circuit constitution for supplying a signal to convey the activation of a row block is not required, and the reduction of area for the semiconductor memory is attained.

Description

technical field [0001] The present invention relates to a semiconductor storage device, and more particularly to a semiconductor storage device such as a DRAM (Dynamic Random Access Memory: Dynamic Random Access Memory) having a sub-amplifier structure. Background technique [0002] JP-A-6-187782 (Patent Document 1) Figure 10 The conventional semiconductor storage device described in is provided with a plurality of memory cell arrays, and a plurality of sense amplifiers in each of the memory cell arrays are provided, through a pair of auxiliary write / read lines and the An auxiliary sense amplifier connected to each sense amplifier, wherein the source of the transistor in the auxiliary sense amplifier is connected to the source of the transistor in each sense amplifier. [0003] However, when the conventional semiconductor storage device adopts the above structure, a precharge circuit must be provided in order to make the sub-input / output line equal to the source voltage of ...

Claims

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Application Information

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IPC IPC(8): H01L21/8242G11C11/409G11C11/4091G11C11/4097H01L27/108
CPCG11C11/4091G11C2207/065G11C11/4097G11C2207/002
Inventor 河野隆司滨本武史
Owner RENESAS ELECTRONICS CORP