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Exposure method for once scanning two common exposure areas

A kind of exposure method, scanning exposure technology

Inactive Publication Date: 2004-12-15
SHANGHAI HUA HONG GROUP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] However, the disadvantage of double exposure technology is that two reticles must be used to expose the same layer twice, doubling the exposure time and halving the machine efficiency, so it will greatly reduce the output and increase the cost, which is not desirable for production; in addition Alignment issues caused by double exposures are also a concern

Method used

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  • Exposure method for once scanning two common exposure areas
  • Exposure method for once scanning two common exposure areas
  • Exposure method for once scanning two common exposure areas

Examples

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Embodiment Construction

[0018] The following example illustrates a possible implementation process of the present invention, the purpose of which is to better explain the application of the present invention, but should not be construed as a limitation of the present invention.

[0019] 1. Load the mask and perform the alignment operation;

[0020] 2. Load silicon wafer and perform alignment operation, calculate compensation amount and set relevant parameters such as scanning distance, step length, scanning origin, etc.;

[0021] 3. Scan the double area, and step into the single area to expose the whole film;

[0022] 4. Repeat 2-3 to complete the exposure of all silicon wafers.

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Abstract

The present invention belongs to the field of photoetching exposure technique in integrated circuit manufacture process, and is especially one kind of exposure method of scanning two common exposure areas simultaneously. Twice exposure technique is attractive for some key layer, and the present invention proposes new exposure method to raise the efficiency of twice exposure. The new exposure method is to scan two areas in once scanning, has greatly raised exposure efficiency, and may find its wide application foreground in integrated circuit manufacture.

Description

technical field [0001] The invention belongs to the photolithographic exposure technology in the integrated circuit manufacturing process, and specifically relates to a new exposure method for scanning two common exposure areas at one time. Background technique [0002] With the continuous development of integrated circuits, the minimum line width of transistors continues to shrink, and the length of transistor gates in advanced CMOS processes is close to 0.1 microns. The continuous reduction of feature line width has led to a substantial increase in chip integration, but the fine lines have brought great challenges to the optical lithography process. [0003] In order to continuously adapt to the reduction of line width and the improvement of integration, the optical lithography technology has been continuously improved: from contact exposure to proximity exposure, and then to reduced projection exposure; the wavelength of the exposure light source is from 430nm of I line t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G03F7/00G03F7/20H01L21/027H01L21/30
Inventor 姚峰英
Owner SHANGHAI HUA HONG GROUP
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