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Filling high aspect ratio isolation structures with polysilazane based material

A technology of group isolation, dielectric material, applied in the field of filling high aspect ratio trenches, can solve the problem of insufficient insulating film

Inactive Publication Date: 2005-02-02
IBM CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If the stress is not what the transistor was designed for, or if the film is etched too fast and removes too much during an etch step that primarily removes another part of the structure, or if the film is etched too quickly during a subsequent critical and unalterable high temperature step is damaged, the process to form an insulating film is insufficient

Method used

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  • Filling high aspect ratio isolation structures with polysilazane based material
  • Filling high aspect ratio isolation structures with polysilazane based material
  • Filling high aspect ratio isolation structures with polysilazane based material

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Embodiment Construction

[0046] The basic sequence in SOD coating is given in Fig. 1, where a set of holes has been etched in a silicon substrate 10 with pad nitride / oxide 20 by any convenient process such as reactive ion etching. The figure shows two sizes of holes for illustration, actual wafers will have various values ​​of hole spacing and hole width and different depths. Variations can arise from fluctuations in a single etching process depending eg on pattern density, or from simultaneous filling of two holes formed in different processes.

[0047] exist Figure 1A To the right of , hole 34 has width 48, depth 46, and an aspect ratio of 46 / 48. The aperture 32 has a width 44, a depth 42, and an aspect ratio of 42 / 44. The aspect ratio of holes 32 is obviously higher than that of holes 34, so the process in question needs to accommodate the range of aspect ratios.

[0048] During this process, a trench dielectric material filling substance known as spin-on-dielectric (SOD) or spin-on-glass (SOG) i...

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Abstract

Isolation trenches and capacitor trenches containing vertical FETs (or any prior levels p-n junctions or dissimilar material interfaces) having an aspect ratio up to 60 are filled with a process comprising: applying a spin-on material based on silazane and having a low molecular weight; pre-baking the applied material in an oxygen ambient at a temperature below about 450 deg C.; converting the stress in the material by heating at an intermediate temperature between 450 deg C. and 800 deg C. in an H2O ambient; and heating again at an elevated temperature in an O2 ambient, resulting in a material that is stable up to 1000 deg C., has a compressive stress that may be tuned by variation of the process parameters, has an etch rate comparable to oxide dielectric formed by HDP techniques, and is durable enough to withstand CMP polishing.

Description

technical field [0001] The field of the invention is the filling of high aspect ratio trenches in integrated circuit processing. Background technique [0002] As the dimensions of the ground rule in integrated circuits shrink, the problem of filling high aspect ratio trenches increases, especially for isolation trenches used in shallow trench isolation (STI), which is commonly used for in advanced processing. [0003] The industry standard filler material and process has been silica, SiO 2 And Deposition High Density Plasma (HDP) technology. This method has been widely adopted as it produces high quality material with good filling properties. Integrated circuit designers have adapted their structural and material specifications to this process and material. [0004] Since silicon is piezoelectric, the characteristics of Field Effect Transistors, FETs, are affected by the stress acting on the body of the transistor. [0005] In the STI process, the isolation trench mater...

Claims

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Application Information

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IPC IPC(8): H01L21/76H01L21/762H01L21/8242H01L27/108
CPCH01L21/76229C10L1/32B01F23/41B01F25/40B01F25/60
Inventor 迈克尔·P·别尔彦斯基拉曼·迪瓦卡若尼拉尔蒂斯·伊科诺米克斯拉甲若·加米小肯尼思·T·赛特米尔帕卓克·C·谢弗
Owner IBM CORP
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