Semiconductor integrated circuit

Abstract

To provide an output circuit having a low parasitic capacitance and resistance in the drains of output transistors, which is operable at a high speed and its ESD performance is improved. A devoted electrostatic discharge protection circuit is provided between the output terminal (pin) and the ground terminal (or power supply terminal). An output circuit which is in parallel connected to this electrostatic discharge protection circuit comprises a first and second MOS transistors which are cascade-connected to each other. The entire area of the source / drain regions of the first and second MOS transistors are silicided. Both transistors have their gate electrodes which are connected to an internal circuit. The source doped region of the first MOS transistor is separated from the drain doped region of the second MOS transistor and they are connected to each other by metal wiring.

Description

Technical field [0001] The present invention relates to a semiconductor integrated circuit, in particular to a semiconductor integrated circuit having a fast output circuit with enhanced antistatic properties. Background technique [0002] MOS transistors constituting semiconductor integrated circuits have been increasingly miniaturized in recent years. With the thinning of the thinner gate insulating film and the shallower junction of the PN junction, the electrostatic protection (ESD protection) of semiconductor integrated circuits is becoming more and more difficult. In order to prevent electrostatic damage, it is indispensable to improve the performance of the ESD protection circuit. of. [0003] With the advancement of miniaturization, in order to make the source and drain diffusion layers low resistance, a technology that uses cobalt silicide or titanium silicide to apply silicidation to the diffusion layer is introduced. However, in MOS transistors that have been subjected...

AI Technical Summary

Problems solved by technology

[0010] In the above-mentioned first prior art example, since the parasitic capacitance of the drain region increases due to the N well provided in the drain region of the output transistor, the switching speed of the transistor becomes slow, and there is a problem that it is impossible to speed up the output circuit.

In the second prior art example, the ESD current flows due to the operation of the parasitic bipolar transistor of the protection element, so when the diffusion layer is silicided, it is necessary to take the same countermeasures as in the first prior art example. There is a problem that the speed of the output circuit cannot be realized

Also, in the second prior art example, the gate electrode of the always-on NMOS transistor is connected to the power supply terminal VDD, so there is a concern that the gate oxide film may be damaged by an ESD strike between the output terminal and the power supply terminal.

Especially in the cutting-edge CMOS technology of the 90nm node with a gate oxide film of about 1.6nm, it is also essential to provide a protection circuit between the output terminal and the power supply terminal, so the protection circuit between the output terminal and the power supply terminal produces The parasitic capacitance also hinders the rapidity of the output circuit

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