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Breakdown test method for medium relative to time in high temperature constant electric field

A dielectric breakdown and testing method technology, applied in the direction of electronic circuit testing, testing dielectric strength, etc., can solve the problems of high cost, short required time, poor error control, etc., and achieve low consumption cost, high testing accuracy, The effect of simple equipment

Inactive Publication Date: 2005-03-02
信息产业部电子第五研究所
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Problems solved by technology

This method is fast, requires a short time, and is simple in equipment. It is suitable for rapid evaluation of process lines on site, but its disadvantages are that the added stress is too large, and the error of extrapolation to normal service conditions is not easy to control. The test results are usually only Can be used as a reference but cannot be quantified
This test method has high precision and accurate test results, but the special test equipment is generally expensive, making the cost relatively high

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  • Breakdown test method for medium relative to time in high temperature constant electric field
  • Breakdown test method for medium relative to time in high temperature constant electric field
  • Breakdown test method for medium relative to time in high temperature constant electric field

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Embodiment Construction

[0017] The time-related dielectric breakdown reliability test method of the present invention also belongs to the package-level test method, and adopts high-temperature constant voltage stress to perform TDDB reliability test on integrated circuit gate oxide layer and dielectric layer test structure. In this embodiment, the test structure uses a thin gate oxide MOS capacitor as the test sample. For the package diagram of the test structure, please refer to figure 1 shown. The test method is carried out as follows:

[0018] Step A: To build a test system, first connect the test structure in parallel, then place the test sample in a high-temperature box, then connect the external resistor in series, and finally connect the external resistor to the test bench, see Figure 2 to Figure 3 As shown, first connect the capacitors in parallel, and resistors are connected in series on both sides of the capacitors in the parallel circuit to limit the current, then put the test sample in ...

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Abstract

The invention is a measuring method for media arcing reliability relating to time. The method uses high temperature constant voltage stress to carry on TDDB reliability measurement to integrated circuit grid oxidizing and media layer measuring structure. The measuring method is carried on according to following steps: constructs the measuring system, at first the measuring structures are connected in parallel, then the sample is put into the high temperature box, and connected to external resistance in series, finally, the external resistance is connected to the measuring desk; puts high temperature and constant voltage stress to the measuring structure; measures the voltage on external resistance, judges if there has measuring structure failure; when some measuring structure is failure, the sample is taken out form the high temperature box, and they are placed on the measuring desk to measure each measuring structure failure or not; records the failure time of each sample according to the failure criterion until the experiment is finished.

Description

【Technical field】 [0001] The invention relates to a testing method, in particular to a testing method for testing the time-related dielectric breakdown reliability of an integrated circuit gate oxide layer and a dielectric layer. 【Background technique】 [0002] There are usually two test methods for the reliability of the time-dependent dielectric breakdown (Time Dependent Dielectric Breakdown, hereinafter referred to as TDDB) of the gate oxide layer and the dielectric layer of the integrated circuit: one is the chip-level test method, and the other is the package-level test method. test method. [0003] The chip-level test method is to use the slope voltage / current or constant voltage / current method for the chip-level test structure to quickly evaluate its TDDB reliability life. This method is fast, requires a short time, and is simple in equipment. It is suitable for rapid evaluation of process lines on site, but its disadvantages are that the added stress is too large, a...

Claims

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Application Information

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IPC IPC(8): G01R31/12G01R31/28
Inventor 罗宏伟
Owner 信息产业部电子第五研究所
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