Breakdown test method for medium relative to time in high temperature constant electric field

A dielectric breakdown and testing method technology, applied in the direction of electronic circuit testing, testing dielectric strength, etc., can solve the problems of high cost, short required time, poor error control, etc., and achieve low consumption cost, high testing accuracy, The effect of simple equipment
CN1588102AInactive Publication Date: 2005-03-02信息产业部电子第五研究所
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Patent Information

Authority / Receiving Office
CN · China
Current Assignee / Owner
信息产业部电子第五研究所
Publication Date
2005-03-02
Estimated Expiration
Not applicable · inactive patent

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Abstract

The invention is a measuring method for media arcing reliability relating to time. The method uses high temperature constant voltage stress to carry on TDDB reliability measurement to integrated circuit grid oxidizing and media layer measuring structure. The measuring method is carried on according to following steps: constructs the measuring system, at first the measuring structures are connected in parallel, then the sample is put into the high temperature box, and connected to external resistance in series, finally, the external resistance is connected to the measuring desk; puts high temperature and constant voltage stress to the measuring structure; measures the voltage on external resistance, judges if there has measuring structure failure; when some measuring structure is failure, the sample is taken out form the high temperature box, and they are placed on the measuring desk to measure each measuring structure failure or not; records the failure time of each sample according to the failure criterion until the experiment is finished.
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Description

【Technical field】

[0001] The invention relates to a testing method, in particular to a testing method for testing the time-related dielectric breakdown reliability of an integrated circuit gate oxide layer and a dielectric layer. 【Background technique】

[0002] There are usually two test methods for the reliability of the time-dependent dielectric breakdown (Time Dependent Dielectric Breakdown, hereinafter referred to as TDDB) of the gate oxide layer and the dielectric layer of the integrated circuit: one is the chip-level test method, and the other is the package-level test method. test method.

[0003] The chip-level test method is to use the slope voltage / current or constant voltage / current method for the chip-level test structure to quickly evaluate its TDDB reliability life. This method is fast, requires a short time, and is simple in equipment. It is suitable for rapid evaluation of process lines on site, but its disadvantages are that the added stress is too large, a...

Claims

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