Integrated circuit chips visual aligning method

A visual alignment, integrated circuit technology, applied in circuits, electrical components, electrical solid devices, etc., can solve the problems of neglecting the positioning error of the chip and the lead frame, limit the calculation speed, reduce the alignment accuracy, etc., to ensure the accuracy, The effect of improving accuracy and reducing measurement errors

Inactive Publication Date: 2005-04-06
HUAZHONG UNIV OF SCI & TECH
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Problems solved by technology

[0011] As a theoretical analysis, the above algorithm proposes some useful alignment algorithms, but it is not closely integrated with the specific production process, and the positioning error between the chip and the lead frame brought about by the SMT process is ignored.
At the same time, the above algorithm only applies to a single alignment mark. If a single mark has a

Method used

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  • Integrated circuit chips visual aligning method
  • Integrated circuit chips visual aligning method
  • Integrated circuit chips visual aligning method

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[0047] The present invention will be further described below in conjunction with the drawings.

[0048] figure 2 The image vision system used in the alignment method of the present invention is shown. After the light emitted from the coaxial lamp 1 is reflected by the elliptical mirror 2, the red light passes through the filter 3. Then the light passes through the homogenizing sheet 4 to form a parallel beam perpendicular to the optical axis, passes through the beam splitter 5, and irradiates the chip surface on the worktable 15 vertically. This light path is a coaxial light path. It produces the best contrast for flat and uniform graphics. In addition to the coaxial lamp 1, four side lamps 8 composed of red-bright light-emitting diode groups are fixed above the workbench 15. They are installed around the coaxial lamp and illuminate the chip at a certain angle. It can produce the best contrast on uneven surfaces and edges. In order to further obtain an image with obvious contras...

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Abstract

It is an integration circuit chip vision aligning method belonging to integration circuit chip seal method, which comprises the following steps: to select sample from the lead wire frame and chip; to get the sample measurement coordinates by image process and to measure the defect chip by image constant moment; to get the chip position transformation parameters to get the coordinates; to get the sample non-linear error by minus measurement coordinates from computation coordinates till the error is within the permitted value; finally to transform the bonding arranged coordinates into bonding workbench displacement coordinates.

Description

technical field [0001] The invention belongs to the packaging method of integrated circuit chips, and specifically relates to the visual alignment method of chips, which is suitable for chip bonding devices, calibration devices, and detection devices, and will be widely used in modern manufacturing industries such as semiconductor equipment, liquid crystal displays, and thin-film magnetic heads. use. Background technique [0002] In the IC and HIC manufacturing industry, the internal interconnection and lead-out wire connection processes of chips mainly include thermocompression welding, silicon-aluminum wire ultrasonic bonding, gold wire ball bonding, flip-chip bonding, and carrier tape bonding. Among them, the gold wire ball bonding process, as one of the main bonding processes, is widely used in the internal leads and lead-out interconnection processes of large-scale integrated circuits and large-scale thick-film hybrid integrated circuits; In the circuit, it is more wid...

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Application Information

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IPC IPC(8): G06F17/50H01L21/60
CPCH01L2924/0002H01L2224/80
Inventor 李小平聂宏飞李朝晖杨文建
Owner HUAZHONG UNIV OF SCI & TECH
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