Integrated circuit chips visual aligning method

Abstract

It is an integration circuit chip vision aligning method belonging to integration circuit chip seal method, which comprises the following steps: to select sample from the lead wire frame and chip; to get the sample measurement coordinates by image process and to measure the defect chip by image constant moment; to get the chip position transformation parameters to get the coordinates; to get the sample non-linear error by minus measurement coordinates from computation coordinates till the error is within the permitted value; finally to transform the bonding arranged coordinates into bonding workbench displacement coordinates.

Description

technical field [0001] The invention belongs to the packaging method of integrated circuit chips, and specifically relates to the visual alignment method of chips, which is suitable for chip bonding devices, calibration devices, and detection devices, and will be widely used in modern manufacturing industries such as semiconductor equipment, liquid crystal displays, and thin-film magnetic heads. use. Background technique [0002] In the IC and HIC manufacturing industry, the internal interconnection and lead-out wire connection processes of chips mainly include thermocompression welding, silicon-aluminum wire ultrasonic bonding, gold wire ball bonding, flip-chip bonding, and carrier tape bonding. Among them, the gold wire ball bonding process, as one of the main bonding processes, is widely used in the internal leads and lead-out interconnection processes of large-scale integrated circuits and large-scale thick-film hybrid integrated circuits; In the circuit, it is more wid...

AI Technical Summary

Problems solved by technology

[0011] As a theoretical analysis, the above algorithm proposes some useful alignment algorithms, but it is not closely integrated with the specific production process, and the positioning error between the chip and the lead frame brought about by the SMT process is ignored.

At the same time, the above algorithm only applies to a single alignment mark. If a single mark has a large local deformation or measurement error, it is still used as an alignment mark, which will significantly reduce the alignment accuracy.

The entire alignment process includes the removal of defective chips such as ink dot marks, edge chipping scratches, and empty chips. The previous algorithm mainly uses a serial calculation process, and the calculation speed is limited.

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