Optimized design method for PN junction underlay isolation on-chip inductance

Abstract

This invention relates to micro electronics technique field and in detail to a method to design the multiple PN joints underlay isolation pad inductance by use of standard CMOS process, which comprises the following steps: to inject impurity with reverse polarity to the trap ions in single trap process; to spread the impurity against top trap to form a PN joint and three serial PN joints vertical to the silicon pad; to control inductance register capacitor through adjusting the single or multiple PN joints isolation layer anti-bias voltage ; to adjust resonance frequency to make the inductance work in self-triggering oscillation frequency.

Description

technical field [0001] The invention belongs to the technical field of microelectronics, and specifically relates to a method for designing a multi-PN junction substrate isolation layer laid under an on-chip inductor by using a standard CMOS process, and a corresponding method for optimizing the inductor. Background technique [0002] With the rapid development of semiconductor technology, monolithic integrated circuits have become possible. Due to the inherent low power consumption, high performance, low cost, and high yield of monolithic integrated circuits, the on-chip implementation of the original off-chip components, such as inductors, has become a research hotspot. Inductors are a key component of radio frequency communications and are widely used in circuits such as amplifiers, mixers, oscillators, and power amplifiers. The rapid development of mobile communication has also greatly promoted the research of on-chip inductors. The characteristics of low power consump...

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Problems solved by technology

However, since the PN junction is formed below it is the active area, which means that the thickness of the oxide layer between the inductor and the substrate is thinner than when nothing is laid, which means that the capacitor C after laying a single layer of PN junction ox will increase, thereby reducing the effect of single-layer PN junction substrate isolation on reducing the parasitic capacitance of the inductor

And the previous practice is that the single-layer PN junction is a whole or simple parallel lines

Since the eddy current direction of the substrate is along the line direction of the inductor, such a structure is not sufficient to prevent the eddy current of the substrate, and since the resistance of the N well is lower than the resistance of the inductor substrate, an effective eddy current will be formed in the N well , increasing the loss of the inductance

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