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SOI field effect transistor element having a recombination region and method of forming same

A technology of field effect transistors and transistors, which is applied in the field of manufacturing these devices and field effect transistors, and can solve problems such as performance degradation of transistor devices, shallow junctions, and transistor size reduction.

Inactive Publication Date: 2005-08-31
ADVANCED MICRO DEVICES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the placement of the SiGe layer in the highly doped source and drain regions may result in a significant increase in resistance in these regions, compromising the performance of the transistor device.
This problem is exacerbated by further shrinking transistor sizes, which require extremely shallow junctions on the source and drain regions

Method used

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  • SOI field effect transistor element having a recombination region and method of forming same
  • SOI field effect transistor element having a recombination region and method of forming same
  • SOI field effect transistor element having a recombination region and method of forming same

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Embodiment Construction

[0023] Specific examples for illustrating the present invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, various implementation-specific decisions must be made to achieve the developer's specific goals, such as conformance with system-related and business-related constraints. , which is a change from one execution to another. All the more appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of the present disclosure.

[0024] The invention will now be described with reference to the accompanying drawings. Although the various structures of semiconductor devices and implanted regions are drawn with very precise and obvious shapes and outlines in the drawings, those skill...

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PUM

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Abstract

An SOI transistor element and a method of fabricating the same is disclosed, wherein a high concentration of stationary point defects is created by including a region within the active transistor area that has a slight lattice mismatch. In one particular embodiment, a silicon germanium layer (320) is provided in the active area having a high concentration of point defects due to relaxing the strain of the silicon germanium layer upon heat treating the transistor element. Due to the point defects, the recombination rate is significantly increased, thereby reducing the number of charged carriers stored in the active area.

Description

technical field [0001] The present invention relates to the field of fabrication of integrated circuits, and more particularly to field effect transistors formed on insulating substrates such as silicon-on-insulator (SOI) devices, and methods of fabricating these devices. Background technique [0002] In modern integrated circuits, the number and thus density of individual circuit components, such as field effect transistors, is constantly increasing, with the result that the performance of these integrated circuits is generally improved. The increase in integrated circuit packaging density and signal characteristics requires the reduction of key structural dimensions such as the gate length of the field effect transistor and the resulting channel length to minimize the chip area occupied by a single circuit component and reduce the size of the chip due to The signal propagation delay formed by the delay channel. However, typical critical structure dimensions are approachin...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L29/786
CPCH01L29/78684H01L29/78612H01L29/66772H01L29/78696
Inventor K·维乔雷克M·霍斯特曼C·克鲁格
Owner ADVANCED MICRO DEVICES INC