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Viterbi decoding based multi-path parallel loop block back trace technique

A technology of decoding and backtracking length, applied in other decoding technologies, error correction/detection using convolutional codes, digital transmission systems, etc., can solve the problems of register exchange algorithm area occupation and high power consumption

Inactive Publication Date: 2005-09-21
BEIJING CEC HUADA ELECTRONIC DESIGN CO LTD
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Problems solved by technology

The register exchange algorithm occupies a huge area and consumes a lot of power, so it is generally not used except for occasions where the code rate is particularly high.

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  • Viterbi decoding based multi-path parallel loop block back trace technique
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  • Viterbi decoding based multi-path parallel loop block back trace technique

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Embodiment Construction

[0023] An implementation example of multi-path parallel loop block backtracking algorithm based on Viterbi decoding. The IEEE802.11a wireless LAN physical layer protocol stipulates that the source of the data sender must pass the convolutional code (133, 171) 8 Encoding, the data receiving end uses this Viterbi backtracking algorithm for decoding, and the decoding structure diagram is shown in the attached figure 1 , the parameters of the Viterbi decoder are set as the backtracking depth T = 96, the backtracking block size S = 32bit, and its decoding performance meets the practical requirements. The specific implementation steps are given below:

[0024] 1. A multi-channel parallel loop block backtracking algorithm based on Viterbi decoding. The branch metric and path metric of Viterbi decoding use the well-known radix-2 butterfly ACS network, and the convolutional code (133, 171) 8If the constraint length is 7, the convolutional code encoder has 6 registers, which are equiv...

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Abstract

A Viterbi decoding based multiplex parallel circular block backtracking algorithm, which contains providing a decoding algorithm only needing to collect convolution code coding backtracking, the backtracking algorithm using single or double RAM whose unit number is constantly the product of two times backtracking depth and the sum of convolution code, the RAM is used by divided into blocks whose number determined by backtracking depth and size of backtracking block, each RAM block corresponding a backtracking unit and backtracking gating network, only part of RAM needed to be accessed, the effective parallel backtracking route number the ratio of backtracking depth and size of backtracking block, in backtracking process, the minimum route measurement value corresponded state value is used as the current state value, finally the backtracking result is arranged in inverted sequence and outputted in normal sequence after being stored.

Description

technical field [0001] A Viterbi decoding scheme for convolutional error correction coding - multi-channel parallel loop block backtracking algorithm, relates to signal processing in communication chips, belongs to the field of wireless communication, and especially relates to area and power consumption optimization for chip design. Background technique [0002] As a forward error correction coding technology, the product code is widely used in wireless communication, mobile communication, deep space communication, and disk storage error correction. However, the decoding of convolutional codes is difficult, and two known methods are algebraic decoding and probability decoding. Algebraic decoding is based on the encoding structure of the convolutional code itself, and the statistical characteristics of the channel are not considered during decoding. Probabilistic decoding should consider the statistical characteristics of the channel when calculating. Typical algorithms suc...

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Application Information

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IPC IPC(8): H03M13/23H03M13/41H04L1/00
Inventor 周斌程东旭
Owner BEIJING CEC HUADA ELECTRONIC DESIGN CO LTD
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