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Method of forming shallow trench isolation structure in a semiconductor device

A semiconductor and device technology, applied in the field of shallow trench isolation structure manufacturing, can solve problems such as connection leakage and device failure

Inactive Publication Date: 2005-11-23
ATMEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Because stress tends to concentrate on the shallow trench corners, the exposed corners 42 can cause connection leakage in the finished device, resulting in device failure

Method used

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  • Method of forming shallow trench isolation structure in a semiconductor device
  • Method of forming shallow trench isolation structure in a semiconductor device
  • Method of forming shallow trench isolation structure in a semiconductor device

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Experimental program
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Embodiment Construction

[0013] see Figure 3A According to the method for forming the shallow trench isolation structure of the present invention, the thermal oxidation of the surface of the silicon substrate 60 can form a thin layer of pad oxide 62 on the upper part of the silicon substrate 60 . A first nitride layer 64 is deposited on top of the pad oxide layer 62 to a thickness typically in the range of 100 Å to 500 Å, and the thickness of the pad oxide layer 62 is typically in the range of 50 Å to 200 Å, followed by a second layer of silicon oxide Layer 66 is deposited, typically at a thickness in the range of 100 Å-300 Å, and a second silicon nitride layer 68, typically at a thickness in the range of 1000 Å-2000 Å. In a typical process, silicon nitride layers 64 and 68 and oxide layer 66 are formed by low pressure chemical vapor deposition (LPCVD). like Figure 3B As shown, trench regions are first formed from a mask (not shown) formed on top of the second silicon nitride layer 68, and then sh...

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PUM

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Abstract

A method (Figs. 3A-3I) for fabricating a shallow trench isolation structure (Fig. 4) is described, in which a bottom pad oxide layer (62), a middle silicon nitride layer (64), a middle oxide layer (66) and a top silicon nitride layer (68) are sequentially formed on a silicon substrate (60). Photo-lithographic masking and anisotropic etching are then conducted to form a trench (70) in the substrate. An oxide material (80) is then deposited on top of the top silicon nitride layer, filling up the trenches at the same time (Fig. 3E). The top silicon nitride layer is then removed, followed by an isotropic etch of the oxide layer below. With the middle nitride layer acting as a natural etch stop, the oxide material is sculpted to a desirable shape. The middle nitride layer and the pad oxide layer are subsequently removed to complete the fabrication of a shallow trench isolation structure.

Description

technical field [0001] The present invention relates to methods of manufacturing integrated semiconductor circuits. In particular, the present invention relates to a method of manufacturing a shallow trench isolation structure. technical background [0002] In high-density packaging integrated circuit manufacturing technology, fabricating shallow trench isolation structures (STI) around active devices is an effective method to prevent the carrier from penetrating from the substrate to adjacent devices. A common process for forming an STI structure is shown in FIG. 1 . In FIG. 1A , a pad oxide layer 12 and a silicon nitride layer 14 are sequentially formed on top of a semiconductor substrate 10 . In FIG. 1B , a shallow trench 16 is formed by photoimaging masking and anisotropic etching of the capping layers 12 , 14 and semiconductor substrate 10 . In FIG. 1C, a thin oxide liner 18 is formed on the bare silicon substrate by thermal oxidation. Subsequently, an oxide materia...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/308H01L21/762
CPCH01L27/11521H01L21/76235H01L21/3081H10B41/30H01L21/76
Inventor T·M·巴里N·德戈D·A·埃里克森A·S·凯尔科B·J·拉森
Owner ATMEL CORP
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