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Manufacturing isolation layer in CMOS image sensor

An image sensor and isolation layer technology, applied in semiconductor/solid-state device manufacturing, electrical solid-state devices, semiconductor devices, etc., can solve problems such as increased junction leakage current, deterioration of image sensor noise characteristics, and silicon lattice etching damage

Inactive Publication Date: 2006-08-16
DONGBUANAM SEMICON
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Problems solved by technology

When a semiconductor substrate is etched, the silicon lattice can suffer etching damage
Also, since the trench is included in the photodiode region, unnecessary interface traps are created at the interface of the STI region
Accordingly, the junction leakage current increases, and the noise characteristics of the image sensor deteriorate

Method used

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  • Manufacturing isolation layer in CMOS image sensor
  • Manufacturing isolation layer in CMOS image sensor
  • Manufacturing isolation layer in CMOS image sensor

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Embodiment Construction

[0017] Reference will now be made in detail to the exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, like reference numbers will be used throughout the drawings to refer to the same or like parts.

[0018] Figures 2A-2C An exemplary method of manufacturing an isolation layer in a CMOS image sensor according to the present invention is described.

[0019] Such as Figure 2A As shown in , the low-concentration P-type epitaxial layer 211 is grown on the high-concentration P-type substrate 210 , and the pad oxide layer 212 is grown on the epitaxial layer 211 . A photoresist (not shown) is coated on the pad oxide layer 212 and exposed and developed to form a photoresist pattern 213 exposing the device isolation region. Using the photoresist pattern 213 as a mask, oxygen ions and high-concentration P-type impurities are sequentially implanted into the epitaxial layer 211 . The semiconductor substrate and th...

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Abstract

A method of manufacturing an isolation layer in a CMOS image sensor injects oxygen and P-type ions into a device isolation region without etching damage and performs a heating process to form a device isolation layer in a semiconductor substrate. An ion injection mask layer is formed that exposes a device isolation region on a low concentration first conductive type semiconductor substrate. Oxygen ions are injected into the semiconductor substrate using the mask layer. A heating process is performed to form an oxide layer in the device isolation region. A gate insulating layer is formed on the semiconductor substrate and a gate electrode is formed on the gate insulating layer. A low concentration second conductive type diffusion region is formed in a photodiode region. A high concentration second conductive type diffusion region is formed at both sides of the gate electrode in the semiconductor substrate. A first conductive type diffusion region haying a concentration higher than that of the semiconductor substrate is formed on the low concentration second conductive type diffusion region in the semiconductor substrate.

Description

[0001] Cross References to Related Applications [0002] This application claims the benefit of Korean Patent Application No. 10-2004-0117225 filed on December 30, 2004, which is hereby incorporated by reference as if fully set forth herein. technical field [0003] The present invention relates to CMOS image sensors, and more particularly, to methods of fabricating isolation layers in CMOS image sensors. The method may implant oxygen and P-type ions into a device isolation region without suffering etching damage and perform a heating process to form a device isolation layer in a semiconductor substrate. Background technique [0004] An image sensor is a semiconductor device for converting an optical image into an electrical signal. A typical complementary metal-oxide-silicon (CMOS) image sensor includes: a charge-coupled device, where charge carriers are stored in metal-oxide-silicon capacitors in close proximity to each other; and MOS transistors corresponding to the numb...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/762H01L21/316
CPCH01L27/1463H01L27/14643H01L27/14689H01L27/146H01L21/76
Inventor 黄俊
Owner DONGBUANAM SEMICON
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