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Semiconductor memory device capable of switching from multiplex method to non-multiplex method

A storage device and semiconductor technology, applied in the direction of information storage, static memory, digital memory information, etc., can solve the problems of expensive test machine, increased test cost, and complicated external command system, and achieve the effect of low test cost and simple design change

Inactive Publication Date: 2006-08-30
RENESAS TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] However, when a semiconductor memory device using a multiplexing method that realizes the sharing of address terminals and data input and output terminals described in this publication is used, even if the terminals are shared, the types of information processed, address signals and data signals are completely different, such as wafer testing. When testing this semiconductor storage device in a test machine, compared with a conventional semiconductor storage device that is not a multiplexing method (hereinafter also referred to as a non-multiplexing method), the external command system becomes very complicated. Completely different test procedures and test fixtures for multiplexed semiconductor memory devices
That is, a tester for a non-multiplexing method, which is a conventional semiconductor storage device, cannot be used, and the tester for this method is very expensive, causing a problem that the test cost increases significantly.

Method used

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  • Semiconductor memory device capable of switching from multiplex method to non-multiplex method
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  • Semiconductor memory device capable of switching from multiplex method to non-multiplex method

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Embodiment 1

[0021] refer to figure 1 , the semiconductor memory device 1 of the embodiment of the present invention has: a memory array 5 with a plurality of memory cells MC arranged in a matrix (not shown); The X decoder 10 of the word line WL corresponding to the cell row; the Y gate circuit 25 controlling the connection of the bit line BL and the write driver / sense amplifier 30 corresponding to the memory cell column on the column side; The internal address signal of the control Y gate circuit Y decoder 15; According to the address signal input by the address pad (terminal), generate the address buffer 20 of the internal address signal; accept the input from the address data multiplexing pad (terminal) The address / data signal is buffered and output after the input, or the data buffer 35 that receives the input of the read data signal output by the write driver / sense amplifier 30 and outputs it to the address data multiplex pad; the output is used for the control device 1 The control p...

Embodiment 2

[0082] In the above-mentioned first embodiment, regarding the generation of the control signal MUX, a mode in which the pad is connected to the ground voltage GND or set in an open state has been described.

[0083] The second embodiment describes the generation of other control signal MUX.

[0084] refer to Figure 7 , the switching control signal generation circuit 42# and Figure 4 Compared with the switching control signal generation circuit 42 described above, the difference is that the fuse 105 connected to the ground voltage GND is provided instead of the mode pad MP, and the inverter 103 is deleted. Other composition and Figure 4 The switching control signal generation circuit 42 described above is the same, and its detailed description is omitted.

[0085] One end of the fuse 105 is connected to the ground voltage GND, and the other end is connected to the input node of the inverter 101 . Can be cut by laser trimming etc.

[0086] For example, when ...

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Abstract

An address pad is independently provided to receive only the address signals independently from an address data multi-pad into which the address signals and the data signals are inputted. The path of the address signals to be inputted to an address buffer is switched by a switching control signal generated in the multiplex system / non-multiplex system. Thus, the address signals and the data signals can respectively be inputted to the address buffer and a data buffer 35 in parallel.

Description

technical field [0001] The present invention relates to a semiconductor memory device, and more specifically, to a semiconductor memory device capable of switching whether or not to use a multiplexing method. Background technique [0002] In recent years, the miniaturization and high integration technology of semiconductor integrated circuits has progressed rapidly, and the increase in capacity and scale of memory devices has been remarkable. Along with this, the number of bits to be processed also increases, and therefore, the number of terminals required for address terminals, data input / output terminals, and the like also tends to increase. [0003] Conventionally, for example, a method of preventing an increase in the number of terminals by sharing terminals in a multiplexing system has been employed. [0004] JP-A-11-306796 discloses an address multiplexing method, and discloses a semiconductor memory device in which address terminals are time-divisionally shared on th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/00G11C11/401
CPCG11C7/1078G11C5/066G11C7/1084G11C7/10
Inventor 藤泽友之久保贵志
Owner RENESAS TECH CORP
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