Duplexing wiring layer and its circuit structure

Abstract

The invention is designed for use in a wafer to define a circuit and a contact window required by next bumping process. The re-wiring layer is located on a wafer's active side and has a line construction mainly comprising a first metal layer, a second metal layer and a conducting layer. Wherein, said conducting layer is mad of aluminum material, and said first and second metal layer are respectively overlapped on each of two side of said conducting layer. The connectivity between the first and second metal layers and a high polymer is higher than the one between said conducting layer and said high polymer. Said first and second metal layer can notably avoid the delaminating between a circuit layer and dielectric layer, and improve the reliability of wafer package.

Description

technical field [0001] The present invention relates to a multi-layer metal layer structure, in particular to an improved redistribution layer (Redistribution layer) and its circuit structure which improves the bonding reliability between the circuit layer and the dielectric layer. Background technique [0002] Flip Chip Interconnect Technology (FC for short) uses an area array to arrange multiple bonding pads on the active surface of a die, and Forming bumps on the bonding pads, and then flipping the chip, using these bumps to electrically and mechanically connect the bonding pads of the chip to the bonding pads (contacts) on the carrier, respectively, The chip can be electrically connected to the carrier through the bump, and electrically connected to the external electronic device through the circuit of the carrier. Since the flip-chip bonding technology (FC) is suitable for high-pin-count (High Pin Count) chip packaging structures, and has many advantages such as reduci...

AI Technical Summary

Problems solved by technology

[0005] It is worth noting that the existing conventional redistribution layer 120 has poor bonding between the circuit layer 124 and the dielectric layers 122, 126, which may easily cause cracks on the bonding surface under the solder bump 132, and the circuit The phenomenon of delamination (peeling) will also occur between the layer 124 and the two adjacent dielectric layers 122 and 126 due to poor bonding, which affects the reliability of the chip package.

[0006] It can be seen that the above-mentioned existing redistributi

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