(First embodiment)
 Hereinafter, while referring to the drawings, a first embodiment of the nitride semiconductor device and the manufacturing method thereof of the present invention will be described.
 First, refer to FIG. 2. FIG. 2 schematically shows a cross-section of a nitride semiconductor device of this embodiment, that is, a GaN-based semiconductor laser. The cross-section of the element shown in the figure is a plane parallel to the end face of the resonator, and the longitudinal direction of the resonator is orthogonal to the cross-section.
 The semiconductor laser of this embodiment includes an n-type GaN substrate (thickness: about 100 μm) 10 doped with n-type impurities, and a semiconductor stacked structure 100 provided on the surface (Ga surface) of the n-type GaN substrate 10.
 The semiconductor laminated structure 100 includes: n-type GaN layer 12, n-type AlGaN cladding layer 14, GaN optical guiding layer 16, InGaN multiple quantum well layer 18, InGaN intermediate layer 20, p-type AlGaN cap layer 22, p-type GaN The light guiding layer 24, the p-type AlGaN cladding layer 26, and the p-type GaN contact layer 28.
 The impurity concentration (dopant concentration) or thickness of each semiconductor layer contained in the semiconductor stacked structure 100 of this embodiment is as shown in Table 1 below.
 Semiconductor layer
 In addition, the impurities, the impurity concentration, and the thickness of each semiconductor layer shown in Table 1 are merely examples, and are not data that limit the present invention.
 The p-type GaN contact layer 28 and the p-type AlGaN cladding layer 26 in the semiconductor laminated structure 100 are processed into the shape of ridge stripes extending along the length direction of the resonator. The width of the ridge stripe is, for example, about 1.5 μm, and the length of the resonator is, for example, 600 μm. The chip width (the element size in the direction parallel to each semiconductor layer in FIG. 5) is, for example, 200 μm.
 Among the upper surface of the semiconductor laminated structure 100, the upper part of the ridge stripe removed is covered with SiO 2 Layer 30 covered in SiO 2 The center of the layer 30 is formed with stripe-shaped openings exposing the upper surface of the ridge stripe. Through SiO 2 In the opening of the layer 30, the surface of the p-type GaN contact layer 28 is in contact with the p-side electrode (Pd/Pt) 32.
 The back surface of the n-type GaN substrate 10 is divided into a rough region 40a where unevenness is formed, and a flat region 40b where unevenness is not formed. An n-side electrode (Ti/Pt/ Au )34. The unevenness steps in the rough region 40a are, for example, in the range of 10 nm or more (preferably 50 nm or more) and 1 μm or less. The unevenness steps in the flat region 40b are, for example, in the range of 1 nm or more and 10 nm or less.
 In this embodiment, the carbon concentration at the interface between the back surface of the n-type GaN substrate 10 and the n-side electrode 34 is reduced to 5 atomic% or less, more specifically, is reduced to 2 atomic% or less.
 Hereinafter, a preferred embodiment of the method of manufacturing the nitride semiconductor device of the present embodiment will be described.
 First, an n-type GaN substrate 10 produced by a known method is prepared. The thickness of the n-type GaN substrate 10 is about 400 μm, for example. The surface of the n-type GaN substrate 10 is flattened by polishing.
 Then, a semiconductor stacked structure 100 is formed on the surface of the n-type GaN substrate 10. The formation of the semiconductor stacked structure 100 can be performed using a known epitaxial growth technique. For example, each semiconductor layer is grown as shown below.
 First, the n-type GaN substrate 10 is inserted into the cell of a metal organic vapor phase growth (MOVPE) device. Thereafter, the surface of the n-type GaN substrate 10 is subjected to heat treatment (thermal cleaning) at about 500 to 1100°C. This heat treatment is performed, for example, at 750°C for 1 minute or more, and preferably for 5 minutes or more. During the heat treatment, it is better to flow a gas (N) containing nitrogen atoms (N) into the chamber. 2 , NH 3 , Hydrazine, etc.).
 After that, the reaction furnace was controlled to a temperature of about 1000°C, while supplying trimethylgallium (TMG) and ammonia (NH) as raw material gases. 3 ), hydrogen and nitrogen as carrier gas, and silane (SiH 4 ) Gas, the growth thickness is about 1μm and the Si impurity concentration is about 5×10 17 cm -3 的n-type GaN layer 12.
 Then, while still supplying trimethyl aluminum (TMA), Al with a thickness of about 1.5 μm and a Si impurity concentration of about 5×1017 cm-3 is grown. 0.05 Ga 0.95 An n-type AlGaN cladding layer 14 made of N. After that, after the GaN layer 16 composed of GaN with a thickness of about 120 nm is grown, the temperature is lowered to about 800°C, the carrier gas is changed to nitrogen, and trimethyl indium (TMI) and TMG are supplied. In about 3nm 0.02 Ga 0.98 Quantum well (3 layers) composed of N and In with a film thickness of about 9nm 0.01 Ga 0.99 A multiple quantum well active layer 18 composed of N barrier layers (two layers). After that, the growth is controlled by In 0.01 Ga 0.99 InGaN intermediate layer 20 made of N. The InGaN intermediate layer 20 can greatly suppress the diffusion of the p-type dopant (Mg) from the p-type semiconductor layer formed thereon to the active layer 18, and the active layer 18 can be maintained at high quality after crystal growth. .
 Then, the temperature in the reaction furnace was raised to about 1000°C again, and hydrogen was introduced into the nitrogen of the carrier gas, and the p-type dopant was supplied with biscyclopentadienyl magnesium (Cp 2 While Mg) gas, the film thickness is about 20nm and the Mg impurity concentration is about 1×10 19 cm -3 Al 0.20 Ga 0.80 A p-type AlGaN cap layer 22 made of N.
 Then, the thickness of the growth is about 20nm and the Mg impurity concentration is about 1×10 19 cm -3 The second GaN optical guiding layer 24 is composed of p-type GaN. Thereafter, the thickness of the growth is about 0.5μm and the impurity concentration is about 1×10 19 cm -3 Al 0.05 Ga 0.95 A p-type AlGaN cladding layer 26 made of N. Finally, the thickness of the growth is about 0.1μm and the Mg impurity concentration is about 1×10 20 cm -3 的p-type GaN contact layer 28.
 Next, referring to FIG. 3(a), the process of forming a plurality of recesses (cleavage guides) 50 on the upper surface of the semiconductor laminate structure will be described. Fig. 3(a) is a plan view of a part of the semiconductor substrate as seen from the upper surface side. The columns of the cleavage guide 50 are periodically arranged on the line where the cleavage should be performed, and function in such a way that the cleavage occurs along the line. The recesses functioning as the cleavage guide 50 have, for example, a depth of 1 to 20 μm, a width of 1 to 5 μm, and a length of 1 to 40 μm, and can be formed by a dicing process and an etching process. In the example shown in FIG. 3(a), the arrangement pitch of the recesses corresponds to the arrangement area of the semiconductor laser element area of the substrate. However, as long as the cleavage can be guided in an appropriate direction, the shape of the recesses or the size of the arrangement pitch may be Arbitrary. However, the concave portion preferably has a rhombus shape having an acute angle in the "cleavage direction" viewed from the upper surface side of the substrate, and the cross-sectional shape perpendicular to the substrate is a hammer shape. This is because when a row of recesses of such a shape is used as a cleavage guide to cleave from the back side of the substrate, it is easy to cleavage straight along the row of recesses, and the material utilization rate of the cleavage is improved.
 After that, the n-type GaN substrate 10 is polished from the back side to reduce the thickness of the n-type GaN substrate 10 to about 100 μm. Then, as shown in FIG. 3(b), after a mask layer 42 having a lattice shape is formed on the back surface of the n-type GaN substrate 10, the area not covered by the mask layer 42 is exposed to an etchant to form Multiple etching pits or protrusions, thereby roughening. As the etching solution, for example, potassium hydroxide (KOH) or hot phosphoric acid can be used. By performing the etching at room temperature for 10 to 60 minutes, a number density of 5×10 can be formed. 6 Pcs/cm 2 , A pit with a depth of 10-1000nm. The roughened area (roughened area 40a) may be formed by dry etching without using the wet etching described above, or by performing dry etching in combination with wet etching.
 The mask layer 42 has a plurality of openings defining the position and shape of the rough region 40a, and can be produced by exposing and developing a resist film, for example. The portion covered by the mask layer 42 in the back surface of the n-type GaN substrate 10 corresponds to the portion where the primary cleavage or the secondary cleavage is performed. An etching pit is not formed in a region not covered by the mask layer 42 in the n-type GaN substrate 10, and functions as a flat region 40b.
 In this embodiment, since the above method is used to form the roughened area 40a in the area on the back surface of the substrate where the n-side electrode 34 should be formed, the area ratio of the N surface in the contact interface is reduced and the surface area is increased. As a result, the carbon concentration of the contact interface can be reduced, and the effective area of contact can be increased. Therefore, the contact resistance can be reduced.
 Thereafter, in the present embodiment, in order to further reduce the contact resistance, an ECR sputtering method is used to deposit SiO with a thickness of about 0.5 to 1.5 μm on the back surface (polished surface) of the n-type GaN substrate 10 2 membrane. By etching the SiO 2 Film, from the back side of the n-type GaN substrate 1O SiO 2 The membrane is removed. SiO 2 The film on the back surface of the n-type GaN substrate 10 needs to be completely removed from at least the region where the n-side electrode should be formed. In this embodiment, hydrofluoric acid is used for SiO 2 Removal of the film. In order to remove SiO 2 The etchant used for the film is not limited to hydrofluoric acid, and other types of etchant may be used. In addition, SiO 2 The removal of the film is not limited to wet etching, and may be dry etching or a combination of wet etching and dry etching. Even if projections and depressions are formed on the back surface of the substrate, a part of the N surface may remain in the rough region 42. Carbon is adsorbed on such N surface, which may deteriorate the contact characteristics. Therefore, it is preferable to perform the above-mentioned back surface treatment (carbon reduction treatment).
 Then, on the back surface of the n-type GaN substrate 10, the respective metal layers of Ti/Pt/Au are successively deposited in this order from the side of the substrate. After that, by removing the mask layer 42, the metal layer on the mask layer 42 is lifted off, and the n-side electrode 34 is formed from the metal layer on the rough region 40 a. After that, a sintering process (about 300°C) was performed in a nitrogen atmosphere. This sintering process has the effect of further reducing the contact resistance of the n-side electrode 34. According to this embodiment, the contact resistivity of the n-side electrode 34 can be set to 5×10 -4 Ω·cm or less.
 According to this embodiment, since the mask layer 42 used in the formation of the rough region 40a is used to pattern the n-side electrode 34, the profile of the contact region between the back surface of the n-type GaN substrate 10 and the n-side electrode 34 is rough. The boundary between the area 40a and the flat area 40b matches.
 FIG. 4 is a cross-sectional view of a part of the n-type GaN substrate 10 at a stage where the n-side electrode 34 is formed. It can be seen from FIG. 4 that the unevenness formed by etching is formed on a part (rough area) of the back surface of the substrate. Such unevenness is composed of facets where crystal planes other than the (000-1) plane are exposed. The rough region of the present embodiment has a plurality of protrusions formed by etching, and each protrusion (height: 10 to 1000 nm) has a polygonal pyramid or a polygonal pyramid shape, and its surface is composed of facets other than the (000-1) plane.
 Then, cleavage is performed once along the broken line shown in FIG. 3(b). FIGS. 5(a) and (b) schematically show the process of forming the strip 10a from the semiconductor substrate by one cleavage. By performing secondary cleavage on the long strip 10a obtained by the primary cleavage, the semiconductor laser shown in FIG. 2 can be obtained. The direction of the secondary cleavage is orthogonal to the direction of the primary cleavage.
 According to this embodiment, since the n-side electrode having the rough region 40a as the contact surface is formed, the effective area of the contact surface can be increased, and the carbon concentration in the contact surface can be reduced, so the n-side electrode can be reduced. Contact resistance. In addition, as shown in FIG. 3(b), since the cleavage guide can be viewed from the back of the substrate, the cleavage can also be performed with excellent material utilization. Furthermore, the flat region 40b on the back surface of the substrate of each semiconductor laser element divided from the substrate by the cleavage is arranged in contact with the cleavage position.
 The flat region 40b on the back surface of the substrate of each semiconductor laser element divided from the substrate by cleavage has a band shape having a width of 20 μm or more, and is located around the rough region 40a (see FIG. 3(b)).
 The arrangement of the flat area 40b on the back surface of the substrate is not limited to the example shown in FIG. 3(b). The flat area 40b may be formed at a position where the cleave guide 50 can be viewed from the back side of the substrate.