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Underfill method

a technology of underfilling and flipchip, which is applied in the direction of basic electric elements, electrical apparatus, and semiconductor devices, can solve the problems of expensive process steps, insufficient amount of underfill material that can be applied without covering solder bumps to form adequate and uniform fillets, and inability to achieve void-free underfills. , to achieve the effect of promoting device reliability

Inactive Publication Date: 2005-01-20
DELPHI TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0011] The present invention provides a process for selectively depositing a filled, wafer-applied underfill onto a die without covering solder bumps present on the die. According to a preferred aspect of the invention, the underfill is a composite underfill comprising multiple different underfill materials that can be deposited prior to die placement. According to another preferred aspect of the invention, the underfill materials are combined in a manner that enables void-free underfilling and ensures the formation of adequate underfill fillets to promote device reliability, and a filler material is incorporated within the underfill to reinforce the solder connections that attach the die to its substrate. The underfilling process of this invention is suitable for use in underfill applications that have previously required capillary-flow underfill materials, as well as those applications in which capillary-flow underfill techniques have been unsuccessful, such as fine-pitch applications.
[0013] The component solder bumps are then registered with the substrate bond pads by pressing the component and its solder bumps into the unfilled underfill material on the substrate. As a result, the filled and unfilled underfill materials combine to form the composite underfill, which fills the space between the component and the substrate and extends onto a peripheral wall of the component. The solder bumps and composite underfill are then heated so that the solder bumps melt and the composite underfill cures to form a composite underfill layer. Finally, the molten solder bumps and the underfill layer are cooled so that the molten solder bumps form solid electrical interconnects that are metallurgically bonded to the bond pads, the composite underfill layer encapsulates the interconnects and defines a fillet that extends onto the peripheral wall of the component, and the space between the component and the substrate is free of voids.
[0014] According to a preferred aspect of the invention, the composite underfill layer is continuous, void-free, and completely fills the space between the component and the substrate. Because the composite underfill layer incorporates a filler material, its CTE is reduced to something close to that of the solder connections it protects, such that the underfill process of this invention is believed to be capable of achieving the product reliability previously possible only with the use of capillary-flow underfill materials and processes, but without the processing costs and limitations associated with capillary-flow underfill materials. Furthermore, because the underfill materials are selectively deposited so as not to cover the solder bumps or the underlying UBM's, the underfill process avoids the prior art practice of using either a burnishing or an ablation technique to re-expose either the solder bumps or UBM's on the die surface prior to die attachment. Finally, the filler material is incorporated within the composite underfill in a manner that promotes reinforcement of the UBM / bump interface, while the unfilled underfill material is primarily responsible for the formation of adequate fillets along the component periphery to promote device reliability.

Problems solved by technology

However, obtaining a void-free underfill using a capillary-flow technique can be difficult if the die has a low standoff height and / or has closely-spaced solder bumps.
In contrast, the microjetting process of U.S. Pat. No. 5,681,757 generally ensures a void-free underfill, but the amount of underfill material that can be applied without covering the solder bumps is insufficient to form an adequate and uniform fillet.
While highly-filled capillary-flow underfill materials have been widely and successfully used in flip chip assembly processes, expensive process steps are typically required to repeatably produce void-free underfills.
These steps can limit the versatility of the flip chip underfill process to the extent that capillary-flow underfilling is not practical for many flip chip applications, especially those chips with fine pitch solder connections and low standoff heights.
However, a drawback of wafer-applied underfilling techniques is that, depending on when the underfill material is applied, the bond pads or the solder bumps present on the wafer or chip must be re-exposed prior to die attachment, such as by burnishing or a laser ablation process.
Furthermore, a drawback of no-flow underfill materials is that they typically do not contain filler materials because of the tendency for the filler particles to hinder the flip chip assembly process.
For example, particles can become trapped between the solder bumps and the bond pads to interfere with the formation of a metallurgical bond, reducing the reliability of the electrical connection.
However, conventional filler levels and filler materials capable of achieving an acceptable CTE for an underfill material are generally incompatible with inkjet technology because of the excessively high viscosity of such materials.

Method used

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Embodiment Construction

[0020]FIG. 3 represents a wafer 11 on which individual dies 10 are delineated by scribe lines 32 (e.g., saw streets), and on which a filled wafer-applied underfill material 14 has been selectively deposited in accordance with the present invention. As illustrated, the invention finds use in the fabrication of semiconductor devices, such that silicon or another semiconductor is a suitable material for the wafer 11 (and therefore the dies 10). Furthermore, the invention finds particular application in the process of attaching flip chips, as represented in FIGS. 4 and 5 in which one of the dies 10 from FIG. 3 is shown being attached to bond pads 18 on a substrate 16. However, other types of devices that are attached by reflowing solder bumps are also within the scope of this invention. It should be noted that the various features of the wafer 11 and dies 10 are not to scale in FIGS. 3 through 6.

[0021] As represented in FIG. 3, the filled underfill material 14 has been selectively depo...

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Abstract

A process for selectively depositing a filled underfill material onto a die surface without covering solder bumps present on the die. The process entails microjetting a polymer matrix material, a filler material, and optionally a fluxing material onto the die surface. Together, the polymer matrix and filler materials define the filled underfill material in which the filler material is dispersed to reduce the coefficient of thermal expansion of the underfill material. The resulting underfill material surrounds but does not cover the solder bumps. The die is then placed on a substrate on which a second underfill material is present, forming a composite underfill layer that completely fills the space between the die and substrate and forms a fillet on a peripheral wall of the die.

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001] Not applicable. STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH [0002] Not applicable. BACKGROUND OF THE INVENTION [0003] (1) Field of the Invention [0004] The present invention generally relates to underfill processes and materials for flip-chip mounted dies. More particularly, this invention relates to a process for selectively depositing a filled, wafer-applied underfill material on a die prior to die attachment and without covering solder bumps present on the die. [0005] (2) Description of the Related Art [0006] Underfilling is well known for promoting the reliability of surface-mount components, such as flip chips (chip scale packages, or CSP's) and ball grid array (BGA) packages, that are physically and electrically connected to traces on organic or inorganic substrates with numerous solder bump connections. Conventional underfill processes generally involve using a specially formulated dielectric material to completely fill the ...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L21/56
CPCH01L21/563Y10T29/49146H01L2224/16225H01L2224/73203H01L2224/83191H01L2224/83192H01L2924/01005H01L2924/01013H01L2924/01033H01L2924/01039H01L2924/01075H01L24/29H01L2224/32225H01L2224/73204H01L24/27Y10T29/4913Y10T29/49144Y10T29/49179Y10T29/49176H01L2224/83193H01L2224/29036H01L2924/00H01L2924/3512H01L2224/73104H01L2924/12042
Inventor WORKMAN, DEREK B.CHAUDHURI, ARUN K.BERG, ERIC M.
Owner DELPHI TECH INC
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