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Semiconductor device

a semiconductor and device technology, applied in the field of semiconductor devices, can solve the problems of reducing the resistance of the charge transfer mos, generating harmonic noise when switching a current, and latching, so as to reduce the resistance of the well region and enhance the robustness against latching

Inactive Publication Date: 2005-03-17
SANYO ELECTRIC CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This invention can solve the issues addressed above, and can provide a semiconductor device structure suitable for a charge pump device with large current capacity and high efficiency.
With a configuration described above, the first buried layer of the first conductivity type reduces a resistance of the well region and robustness against latch up can be enhanced. And the well region of the first conductivity can be set at desired potential independent from the single crystalline semiconductor substrate because of the second buried layer of the second conductivity type.
And with the configuration described above, a back gate bias effect of the MOS transistor can be suppressed when the drain layer of the MOS transistor and the well region of the first conductivity are electrically connected.

Problems solved by technology

However, it has a drawback to generate a harmonic noise when switching a current.
The first issue is to reduce ON resistance of a charge transfer MOS transistor so that the charge pump circuit can provide a high voltage (over 10V) and a large current (several milliamperes) required to the power supply circuit.
The second issue is to prevent a latch up, which often happens to a high current charge pump device.
Especially, there has been a problem with a large current charge pump device to cause a latch up at the beginning of the operation.
However, following inequalities hold at start-up of the charge pump device (at the beginning of the voltage boosting).

Method used

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first embodiment

Next, this invention will be explained referring to FIGS. 1-4. First, a structure of a BiCMOS device, with which a charge pump device is implemented in an integrated circuit, will be explained referring to FIG. 1.

Each of an N-channel MOS transistor (NMOS), P-channel transistor (PMOS) and an NPN bipolar transistor (NPN Tr) is formed in each of predetermined regions in an N-type epitaxial silicon layer 51, having resistivity of 1.25 Ωcm, for example, grown by vapor phase epitaxy on a P-type single crystalline silicon substrate 50.

The N-channel MOS transistor is formed in a P-type well region 52 formed in a surface of the N-type epitaxial silicon layer 51. The P-type well region 52 is, for example, about 2 μm deep. The N-channel MOS transistor has an N+-type drain layer D, an N+-type source layer S, both formed in the surface of the P-type well region 52, and a gate electrode G formed on a gate insulation film. The N-channel MOS transistor can be formed in a so-called LDD structure ...

second embodiment

FIG. 5 is a cross-sectional view showing a charge pump device according to this invention.

Circuit structure of this charge pump device is similar to that of the first embodiment. The charge transfer MOS transistors M2 and M3 of the charge pump device of FIG. 19 are shown in FIG. 5, as in the case of the first embodiment.

Difference from the first embodiment is that the P+-type buried layer 55 is not formed below the P-type well regions 52A and 52B. Although the effect to reduce the resistance of the P-type well regions 52A and 52B is lost because of the lack of the P+-type buried layer 55, it seems that robustness against latch up is increased compared with the conventional charge pump device by adding the lower isolation layer 58 and the upper isolation layer 59.

third embodiment

FIG. 6 is a cross-sectional view showing a charge pump device according to this invention.

Circuit structure of this charge pump device is similar to that of the first embodiment. The charge transfer MOS transistors M2 and M3 of the charge pump device of FIG. 19 are shown in FIG. 6.

Difference from the first embodiment is that neither the N+-type buried layer 56 nor the P+-type buried layer 55 is formed below the P-type well regions 52A and 52B.

Although the effect to reduce the resistance of the N-type epitaxial silicon layers 51 is lost because of the lack of the N+-type buried layer 56, it seems that robustness against latch up is increased compared with the conventional charge pump device by adding the lower isolation layer 58 and the upper isolation layer 59.

Next, a fourth embodiment of this invention will be explained referring to FIGS. 7-17. In the charge pump device of this embodiment, a voltage from a level shift circuit is applied to a gate of a charge transfer MOS tra...

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Abstract

A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. An N-type epitaxial silicon layer is formed on a P-type single crystalline silicon substrate, and a P-type well region is formed in the N-type epitaxial silicon layer. A P+-type buried layer abutting on a bottom of the P-type well region and an N+-type buried layer partially overlapping with the P+-type buried layer and electrically isolating the P-type well region from the single crystalline silicon substrate are formed. And then, an MOS transistor is formed in the P-type well region.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a semiconductor device, specifically to a charge pump device with large current capacity used for a power supply circuit. Performance of the charge pump device can be improved and a latch up can be prevented with this invention. 2. Description of the Related Art Video equipment in recent years such as a camcorder, a digital still camera (DSC) and a mobile phone with DSC use CCDs (charge-coupled devices) to capture an image. A CCD drive circuit for driving the CCDs requires a power supply circuit that provides both positive and negative high voltages (over 10 volts) and a large current (several milliamperes). A switching regulator is used for that purpose today. The switching regulator can generate a high voltage with high performance, i.e. with high power efficiency (output power / input power). However, it has a drawback to generate a harmonic noise when switching a current. Therefore, the power supp...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L21/822H01L27/04H01L21/8238H01L21/8249H01L27/02H01L27/06H01L27/092H03K19/0185
CPCH01L21/823892H01L21/8249H01L27/0921H01L27/0623H01L27/0222H01L29/78
Inventor KANEKO, SATORUOHKODA, TOSHIYUKIMYONO, TAKAO
Owner SANYO ELECTRIC CO LTD
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