Signal-processing apparatus and electronic apparatus using same

a technology of electronic equipment and processing equipment, applied in the direction of multiple processing units, instruments, television systems, etc., can solve the problems of large processing amount, inability to mount to the built-in system, and inability to improve the processing efficiency of calculators

Inactive Publication Date: 2005-03-24
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the newly introduced coding tools adopt algorithms attaching importance to the coding efficiently; therefore, the processing amount is large and mounting to the built-in system is difficult.
However, according to the MPEG-4 AVC, since the smallest sub-macro-block size is 4×4 pels, with the prior signal-processing apparatus, the processing efficiency of the calculators does not improve even if 16 or more parallel calculators are provided.
Moreover, in the arithmetic coding/decoding processing of the MPEG-4 AVC, since the processing is performed while the probability of occurrence is changed in accordance with the contexts of peripheral macro-blocks, it is necessary to perform coding bit by bit, which means the parallel processing cannot be performed.
That is, with the prior signal-processing apparatus, the processing performance in the MPEG-4 AVC cannot be improved even if the degree of parallelism of the MIMD parallel data processor is enhanced.
When an SIMD calculator is used, although filtering proce

Method used

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  • Signal-processing apparatus and electronic apparatus using same

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first embodiment

(First Embodiment)

FIG. 1 is the block diagram of the signal-processing apparatus in the first embodiment of the present invention. The signal-processing apparatus of the present embodiment comprises: an instruction-parallel processor 100 having a local memory 110; a first data-parallel processor 101 having a local memory 111; a second data-parallel processor 102 having a local memory 112; a motion detection unit 103 having a local memory 113; a de-blocking filtering unit 104 having a local memory 114; a variable-length coding / decoding unit 105 having a local memory 115; an input and output interface 106 having a local memory 116; a first shared memory 121; a first instruction bus 130; and a first data bus 132. The processors 100 to 102 and the units 112 to 116 are connected to the first instruction bus 130, and the local memories 110 to 116, the first shared memory 121 and the input and output interface 106 are connected to the first data bus 132. The variable-length coding / decoding...

second embodiment

(Second Embodiment)

FIG. 2 is the block diagram of the signal-processing apparatus in the second embodiment of the present invention. In FIG. 2, components similar to those of FIG. 1 are denoted by the same reference numerals, and descriptions thereof are omitted.

The signal-processing apparatus of the present embodiment further comprises, compared to the signal-processing apparatus of the first embodiment, a control processor 107, a second shared memory 122, a second instruction bus 131, a second data bus 133, and a bridge unit 120 connecting the first data bus 132 and the second data bus 133.

The instruction-parallel processor 100, the control processor 107 and the variable-length coding / decoding unit 105 are connected to the first instruction bus 130.

The control processor 107, the first data-parallel processor 101, the second data-parallel processor 102, the motion detection unit 103 and the de-blocking filtering unit 104 are connected to the second instruction bus 131.

The l...

third embodiment

(Third Embodiment)

FIG. 3 is the block diagram showing a video encoder in the third embodiment of the present invention.

The video encoder of the present embodiment is an encoder capable of the MPEG-4 AVC. Each component is given a name adequately expressing a function of the video encoder corresponding to the MPEG-4 AVC.

The video encoder of the present embodiment shown in FIG. 3 comprises the signal-processing apparatus of the second embodiment. Therefore, the correspondence between the components of FIG. 3 and the components of FIG. 2 will be shown first.

The processing of a coding controller 301 and a mode switcher 303 are performed by the instruction-parallel processor 100 of FIG. 2.

The processing of a motion compensator 312 and a difference detector 302 are performed by the first data-parallel processor 101 of FIG. 2.

The processing of a 4×4 DCT transformer 304, a quantizer 305, an inverse quantizer 306, an inverse 4×4 DCT transformer 307 and a reconstructor 309 are perfo...

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Abstract

A signal-processing apparatus comprises an instruction-parallel processor, a first data-parallel processor, a second data-parallel processor, and a motion detection unit, a de-blocking filtering unit and a variable-length coding/decoding unit which are dedicated hardware. With this structure, in signal processing of an image compression and decompression algorithm with a large processing amount, the load is distributed between software and hardware, so that the signal-processing apparatus can realize high processing capability and flexibility.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal-processing apparatus that performs audio and image compression / decompression at high speed by use of a parallel processor and dedicated hardware, and an electronic apparatus using the same. 2. Description of the Related Art In response to the recent trend toward higher performance and downsizing of image processing apparatuses and image display apparatuses that handle moving images, the ISO (International Organization for Standardization) and the ITU-T (International Telecommunication Union-Telecommunication Standardization Sector) are co-planning the standardization of MPEG-4 AVC (Advanced Video Coding) as a next-generation compression and decompression technology. The MPEG-4 AVC realizes a high image compression rate by introducing new technologies such as integer conversion of 4×4 pixels, intra prediction at up to nine directions, seven kinds of sub-macro-block types, up to 16 moti...

Claims

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Application Information

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IPC IPC(8): G06T1/60G06F15/80G06T1/20H04N5/92H04N7/24H04N19/136H04N19/42H04N19/436H04N19/50H04N19/503H04N19/51H04N19/523H04N19/61H04N19/625H04N19/70H04N19/80H04N19/91
CPCH04N19/61H04N19/44H04N19/86H04N19/436H04N19/523H04N19/42G06F9/3885G06F9/3877
Inventor KATAOKA, TOMONORINISHIDA, HIDESHIKIMURA, KOUZOUHIGAKI, NOBUOKIYOHARA, TOKUZU
Owner PANASONIC CORP
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