Signal-processing apparatus and electronic apparatus using same

Abstract

A signal-processing apparatus comprises an instruction-parallel processor, a first data-parallel processor, a second data-parallel processor, and a motion detection unit, a de-blocking filtering unit and a variable-length coding / decoding unit which are dedicated hardware. With this structure, in signal processing of an image compression and decompression algorithm with a large processing amount, the load is distributed between software and hardware, so that the signal-processing apparatus can realize high processing capability and flexibility.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal-processing apparatus that performs audio and image compression / decompression at high speed by use of a parallel processor and dedicated hardware, and an electronic apparatus using the same. 2. Description of the Related Art In response to the recent trend toward higher performance and downsizing of image processing apparatuses and image display apparatuses that handle moving images, the ISO (International Organization for Standardization) and the ITU-T (International Telecommunication Union-Telecommunication Standardization Sector) are co-planning the standardization of MPEG-4 AVC (Advanced Video Coding) as a next-generation compression and decompression technology. The MPEG-4 AVC realizes a high image compression rate by introducing new technologies such as integer conversion of 4×4 pixels, intra prediction at up to nine directions, seven kinds of sub-macro-block types, up to 16 moti...

AI Technical Summary

Benefits of technology

An object of the present invention is to provide a signal-processing apparatus capable of performing high-performance and high-efficiency image processing for image processing requiring a large data processing amount like the coding / decoding processing of the MPEG-4 AVC, and an electronic apparatus using the same.

According to the present structure, the AV signals can be efficiently encoded / decoded at high speed, and the electronic apparatus with a low power consumption, into which a recording function and a reproduction function are integrated, can be realized.

Problems solved by technology

However, the newly introduced coding tools adopt algorithms attaching importance to the coding efficiently; therefore, the processing amount is large and mounting to the built-in system is difficult.

However, according to the MPEG-4 AVC, since the smallest sub-macro-block size is 4×4 pels, with the prior signal-processing apparatus, the processing efficiency of the calculators does not improve even if 16 or more parallel calculators are provided.

Moreover, in the arithmetic coding / decoding processing of the MPEG-4 AVC, since the processing is performed while the probability of occurrence is changed in accordance with the contexts of peripheral macro-blocks, it is necessary to perform coding bit by bit, which means the parallel processing cannot be performed.

That is, with the prior signal-processing apparatus, the processing performance in the MPEG-4 AVC cannot be improved even if the degree of parallelism of the MIMD parallel data processor is enhanced.

When an SIMD calculator is used, although filtering processing can be performed in parallel, the calculators cannot be effectively used in determination processing.

Moreover, with the signal-processing apparatus comprising a combination of the SIMD data-parallel processor and the dedicated hardware is typified by the above-described Document 2, although the processing performance is improved by adopting the dedicated hardware for the arithmetic coding / decoding processing that requires high processing performance, performing motion detection with the largest processing amount by the SIMD parallel data processor causes the following problem.

The capability of the SIMD parallel data processor having such capability is more than enough in the decoding processing; therefore, the entire processor can not be efficiently used.

Furthermore, even if it is attempted to improve the processing performance by enhancing the degree of parallelism of the SIMD parallel data processor, since the block size is 4×4 pels, it is impossible for the degree of parallelism to be more than 16.

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