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Digital reliability monitor having autonomic repair and notification capability

a digital reliability monitor and autonomic repair technology, applied in error detection/correction, instruments, generating/distributing signals, etc., can solve problems such as difficult compensation and reliability degradation, and achieve the effect of preventing the failure of an integrated circui

Inactive Publication Date: 2005-06-30
GLOBALFOUNDRIES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention provides an integrated circuit with a repair processor that can replace the original circuit with a redundant circuit when the original circuit fails. The repair processor includes a clock cycle counter that counts the pulses of a pulsed signal and a stress reduction circuit that modifies the operating parameters of the original circuit when the clock cycle counter reaches a particular pre-determined cycle count. This invention prevents failure of the integrated circuit and increases its reliability.

Problems solved by technology

Such degradations in reliability caused by technology features needed to improve performance are difficult to compensate for with current integrated circuit design techniques.

Method used

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  • Digital reliability monitor having autonomic repair and notification capability
  • Digital reliability monitor having autonomic repair and notification capability
  • Digital reliability monitor having autonomic repair and notification capability

Examples

Experimental program
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Effect test

first embodiment

[0031]FIG. 1 is a schematic block diagram of an integrated circuit according to the present invention. In FIG. 1, an integrated circuit chip 100 includes a system clock generator 105, a clock cycle counter 110, a redundant clock cycle counter 110A, a repair processor 115, an optional fuse bank 120, an original circuit 125 and a multiple of redundant circuits 125A through 125N, each redundant circuit capable of performing the same function as the original circuit. There may be only one redundant circuit. Additionally, integrated circuit 100 may include an on-chip count memory 130 for storing the cumulated number of cycles counted by clock cycle counter 110. Alternatively, the count memory 130 may be implemented off-chip.

[0032] System clock generator (which may be a PLL circuit) generates a clock signal CLK supplied to original circuit 125 and a multiple of redundant circuits 125A through 125N and to clock cycle counter 110. Clock cycle counter 110 keeps a running tally of the number ...

second embodiment

[0034] It should be noted, that clock cycle counter 110 may be repairable using the present invention. To this end, repair processor 115 can automatically insert redundant clock cycle counter 110A between system clock generator 105, memory counter 130 and the repair processor itself in place of clock cycle counter 110 when a predetermined number of clock cycles are reached. This pre-determined number of clock cycles should be significantly less than the COUNTA signal value. More than one redundant clock cycle counter may be provided and this process may be repeated as many times as there are redundant repair processors FIG. 2 is a schematic block diagram of an integrated circuit according to the present invention. In FIG. 2, integrated circuit 135 is similar to integrated circuit 100 of FIG. 1, except original circuit 125 and redundant circuits 125A through 125N of FIG. 1 are replaced with a field programmable gate array (FPGA) 140. A portion 145 of FPGA 140 is reserved for use as r...

fourth embodiment

[0054]FIG. 12 is a schematic block diagram of an integrated circuit according to the present invention. In FIG. 12, a data in signal is applied to the input of a multiplexer 500. The inputs of an original circuit 505, a multiplicity of redundant circuits 510 and a robust redundant circuit 515 are each connected to a different output of multiplexer 500. The output of original circuit 505, of redundant circuits and robust redundant circuit 515 are each connected to a different input of demultiplexer 520. The output of demultiplexer 520 is a data out signal. Multiplexer 500 and demultiplexer 520 are responsive to control signals 525A and 525B generated by a clock cycle counter and repair processor 530 that are applied respectively to the control inputs of multiplexer 500 and demultiplexer 520. Clock cycle counter and repair processor 530 receives a CLK signal.

[0055] In operation, when clock cycle counter and repair processor 530 counts a predetermined number of clock cycles, control si...

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PUM

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Abstract

A method a circuit for preventing failure in an integrated circuit. The circuit including: an original circuit; one or more redundant circuits; and a repair processor, including a clock cycle counter adapted to count pulses of a pulsed signal, the repair processor adapted to (a) replace the original circuit with a first redundant circuit or (b) adapted to select another redundant circuit, the selection in sequence from a second redundant circuit to a last redundant circuit, and to replace a previously selected redundant circuit with the selected redundant circuit each time the cycle counter reaches a predetermined count of a set of predetermined cycle counts.

Description

REFERENCES TO PRIOR APPLICATIONS [0001] The present application is a continuation-in-part of application Ser. No. 10 / 729,751 filed on Dec. 4, 2003.FIELD OF THE INVENTION [0002] The present invention relates to the field of fault tolerance in integrated circuits; more specifically, it is directed toward a circuit structure and method for repairing integrated circuit elements prior to failure, and a method of designing an integrated circuit with autonomic repair capability. BACKGROUND OF THE INVENTION [0003] As the frequency performance of integrated circuits continues to increase, the rate of certain failure mechanisms increases in proportion to operating frequency, thereby reducing the time over which an integrated circuit can be expected to reliably perform. Such degradations in reliability caused by technology features needed to improve performance are difficult to compensate for with current integrated circuit design techniques. Therefore, a structure and method for mitigating th...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F1/04
CPCG06F1/04
Inventor BONACCIO, ANTHONY R.LESTRANGE, MICHAELTONTI, WILLIAM R.VENTRONE, SEBASTIAN T.
Owner GLOBALFOUNDRIES INC
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