Semiconductor chip and fabrication method thereof

Abstract

A semiconductor chip and a fabrication method thereof are disclosed. In the fabrication method, isotropic etching and anisotropic etching are performed on a cutting portion of a semiconductor wafer to form grooves in the semiconductor wafer. Through these grooves, the semiconductor wafer can be diced with no use of any dicing blade. In addition, it is possible to form semiconductor chips whose edges and corners are rounded off. According to the fabrication method, fabrication time can be shorten. In addition, it is possible to improve integration and yield of semiconductor chip formation.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention is related to a method of fabricating semiconductor chips by dicing a semiconductor wafer at a predetermined size. [0003] 2. Description of the Related Art [0004] In a conventional semiconductor chip fabrication process, a semiconductor wafer, on which a plurality of semiconductor elements are formed, is diced in a dicing process of the fabrication process by shifting a rotationally-driven disk-shaped cutter (dicing blade) of a semiconductor chip fabrication apparatus vertically and horizontally so as to form a large number of semiconductor chips. In general, such semiconductor chips are box-shaped. [0005] In the above-mentioned conventional semiconductor chip fabrication process, since a dicing blade of a semiconductor chip fabrication apparatus is shifted vertically and horizontally to dice a semiconductor wafer, the semiconductor chip fabrication apparatus has to perform a greater number of ...

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Benefits of technology

[0008] It is a general object of the present invention to provide a novel and useful semiconductor chip and fabrication method thereof in which one or more of the above-mentioned problems are eliminated.

Problems solved by technology

Thus, it takes more dicing time to produce more semiconductor chips.

In general, an interval between adjacent semiconductor chips has to be set as more than the dicing line width of about 50 μm, and this requirement adversely influences high-density semiconductor chip formation on a semiconductor wafer.

Such a thin semiconductor wafer is fragile to a dicing blade.

Such a box-shaped semiconductor chip has a significant problem in that a corner and an edge of the semiconductor chip may be chipped when the semiconductor chip is handled or carried, resulting in yield reduction thereof.

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