Plating apparatus and method

Abstract

The present invention comprises a metal plating apparatus and method, particularly suitable for autocatalytic (i.e., electroless) plating, comprising a pressurized sealable vessel for disposing a substrate to be plated and for the circulation of plating solutions wherein temperatures and pressure are highly controllable.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application claims the benefit of the filing of U.S. Provisional Patent Application Ser. No. 60 / 541,687, entitled “Pressurized Autocatalytic Vessel and Vacuum Chuck”, filed Feb. 4, 2004. This application is also related to U.S. patent application Ser. No. 10 / 778,647, entitled “Apparatus and Method for Highly Controlled Electrodeposition”, filed Feb. 12, 2004, which claims priority of U.S. Provisional Patent Application Ser. No. 60 / 447,175, entitled “Electrochemical Devices and Processes”, filed Feb.12, 2003, and which is a continuation-in-part application of U.S. patent application Ser. No. 10 / 728,636, entitled “Coated and Magnetic Particles and Applications Thereof”, filed Dec.5, 2003, which claims priority of U.S. Provisional Patent Application Ser. No. 60 / 431,315, entitled “Solid Core Solder Particles for Printable Solder Paste”, filed on Dec. 5, 2002, and the specifications and claims thereof are incorporated herein by referenc...

AI Technical Summary

Benefits of technology

[0050] A primary advantage of the present invention is the ability to finely control the plating processes with regard to, but not limited to, initiation rates, deposition rates, temperature control, and pressure control.

[0051] Another advantage of the present invention is the ability to reduce the volumes required for plating.

[0052] Another advantage of the present invention is the ability to minimize the risks of damage in plating small, expensive substrates and thus reduce the costs inherent in such damage.

Problems solved by technology

However, it is difficult to control spurious and extraneous metal deposition onto surface areas where the metal is not desired.

At micron and submicron feature sizes, the magnitude of plating resolution and definition errors can approach, and even exceed, the feature separation distance.

This can cause conductor bridging and electrical shorting of the wafer or substrate.

However, the addition of inhibitors can negatively impact the utility of plating for subsequent joining / connecting procedures.

This effect has discouraged the wide use of conventional electroless plating technology for wafer scale electronic joining applications.

The requirement to physically move the wafer or substrate from tank to tank creates a significant risk of damage to the wafer.

The risk of damage is increased by the ongoing trend in the semiconductor processing industry to “thin” wafers by chemical or mechanical means, making an already delicate structure even more fragile.

With respect to the electrolytic plating of thin wafers such as those found in the semiconductor industry, the existing electrolytic plating methodology suffers from certain limitations.

Such build-up detrimentally fuses the contact point to the surface of the wafer and at the completion of the process can result in a tearing or removal of the deposited film at the contact point.

Another limitation of electrolytic plating is that the resulting surface area of the exposed contact can greatly affect the amperage density applied and the cathode efficiency of the wafer, which must be strictly controlled.

This causes inaccurate or inconsistent results in the mean target thickness of the deposited film.

The existing designs for electrolytic plating require a chemical contact point and therefore create limitations in the number of contact points that can be supplied around the periphery and effectively sealed to prevent a detrimental influence on the surface area of the plated wafer.

A limitation of copper electro-deposition on silicone wafers is that the copper electrolyte and the resulting copper deposit can contaminate the silicon.

This converts the semiconductor material into a conductive material, thereby ruining the entire wafer by converting the surface from insulator to conductor.

Such devices are fairly complicated in that typically a sandwich comprising a back plate, an O-ring seal, and a top frame must be clamped, bolted, or fixed to the wafer.

This limits the effectiveness of automating the wafer handling process in a production environment.

Consequently, the complicated nature of such devices limits the cross-sectional area of the bussing elements which connect to the contact points.

The resulting buss cross-section is reduced to favor the mechanical design, which detrimentally affects impacity or current carrying capacity.

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