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Cluster based non-volatile memory translation layer

a non-volatile memory and translation layer technology, applied in the field of integrated circuits, can solve the problems of no longer properly removing the charge from the floating gate, unable to properly erase the data in the ram, and unable to achieve the effect of fast scanning

Inactive Publication Date: 2006-03-02
MICRON TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0010] The various embodiments relate to non-volatile memory devices and memory subsystems that utilize cluster based logical block / sector to physical block / sector address translation. As stated above, the translation of logical blocks / sectors to the physical blocks / sectors by a controller and / or software / firmware is necessary for a non-volatile memory to appear as a freely rewriteable device to the system or processor that it is coupled to. The controller or firmware responsible for this translation is called the translation layer (TL). Embodiments of the present invention utilize cluster based address translation to translate logical block addresses to physical block addresses, wherein each cluster contains a plurality of sequentially addressed logical blocks. Cluster address translation closely represents the actual data storage use of the file system and its logical block use / grouping. This allows the use of a smaller RAM table for the address translation lookup and / or faster scanning of the memory device or memory subsystem for the matching cluster address. In one embodiment, variable cluster granularity (an adjustable number of blocks / sectors per cluster) allows the non-volatile memory storage to closely match its use and the data that will be stored in it. In another embodiment of the present invention, a specially formatted cluster is utilized for frequently updated sectors / logical blocks, where the cluster stores a single sector / logical block and new sequential physical sectors / blocks of the cluster is written in turn with each new update of the logical block and the previous physical block holding the old data invalidated until the entire cluster has been used. This allows multiple updates of a logical sector without having to move and invalidate / erase the cluster containing the old data.

Problems solved by technology

Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents.
As soon as the power is turned off, whatever data was in RAM is lost.
Write fatigue is where the floating gate memory cell, after repetitive writes and erasures, no longer properly erases and removes charge from the floating gate.
With the data storage capacity of modern Flash memories increasing issues are being caused with the size of the required RAM table and / or the time required to scan the Flash memory for the requested sector.
This is particularly an important issue in resource limited handheld or embedded devices.

Method used

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Embodiment Construction

[0023] In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the inventions may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the spirit and scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the claims.

[0024] To overcome the reliance on conventional logical block to physical block RAM address translation tables or physical block scans with the above detailed issues of large RAM footprints and / or time consuming physical scans a non-volatile memory of the pres...

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PUM

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Abstract

An improved non-volatile memory and logical block to physical block address translation method utilizing a cluster based addressing scheme is detailed. The translation of logical blocks / sectors to the physical blocks / sectors is necessary for a non-volatile memory to appear as a freely rewriteable device to a system or processor. Embodiments of the present invention utilize cluster based address translation to translate logical block addresses to physical block addresses, wherein each cluster contains a plurality of sequentially addressed logical blocks. This allows the use of a smaller RAM table for the address translation lookup and / or faster scanning of the memory device or memory subsystem for the matching cluster address. In one embodiment, a specially formatted cluster is utilized for frequently updated sectors / logical blocks, where the cluster stores a single logical block and a new sequential physical block of the cluster is written in turn with each update.

Description

TECHNICAL FIELD OF THE INVENTION [0001] The present invention relates generally to integrated circuits and in particular the present invention relates to sector address translation of non-volatile memory devices. BACKGROUND OF THE INVENTION [0002] Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory used in modern electronics, one common type is RAM (random-access memory). RAM is characteristically found in use as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to ROM, which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost. [0003] Computers almost always c...

Claims

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Application Information

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IPC IPC(8): G11C8/00
CPCG06F2212/7201G06F12/0246
Inventor WONG, WANMOJAHN, MARKSEPULVEDA, FRANK
Owner MICRON TECH INC
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