Semiconductor integrated circuit device

Abstract

Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micropatterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

Description

[0001] This application is a Continuation of application Ser. No. 11 / 042,172, filed Jan. 26, 2005 which is a Continuation of application Ser. No. 10 / 606,954, filed Jun. 27, 2003 (now abandoned), which is a Continuation of application Ser. No. 09 / 565,535, filed May 5, 2000 (now U.S. Pat. No. 6,677,649), the entire disclosures of which are hereby incorporated by reference.BACKGROUND OF THE INVENTION [0002] The present invention relates generally to semiconductor integrated circuit devices and, more particularly, to layout schemes of static random access memory (SPAN) cells. The invention also relates to semiconductor memory devices using such cells. [0003] One-port SRAM cells with complementary metal oxide semiconductor (CMOS) configurations are typically designed so that each cell consists essentially of six separate transistors. An exemplary layout of such cells has been disclosed, for example, in JP-A-10-178110 (laid open on Jun. 30, 1998). [0004] In the previously known SRAM cell ...

AI Technical Summary

Problems solved by technology

Unfortunately, the requirements for micro-patterning architectures have grown more rapidly than technological advance in the trend of shortening wavelengths in such equipment.

This makes it impossible, or at least very difficult, to microfabricate ultrafine layout patterns while disadvantageously serving as the cause of the destruction of the symmetry of memory cells.

Thus, the prior art suffers from the problem of the degradation of the symmetrization of the cell layout pattern, making the successful achievement of microfabrication architectures for higher integration densities difficult.

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