Delay stage-interweaved analog DLL/PLL

a delay stage and analog technology, applied in the field of memory systems, can solve the problems of increasing the corresponding overall delay, vcdl may not properly function at low input clock frequency, and it is not possible to obtain a delay range of 1 ns, so as to achieve a wide frequency range of operation, reduce current consumption, and fast lock time

US20060087908A1Active Publication Date: 2006-04-27MICRON TECH INC
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Patent Information

Authority / Receiving Office
US · United States
Patent Type
Applications(United States)
Current Assignee / Owner
Publication Date
2006-04-27

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Abstract

A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
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Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is a divisional of U.S. application Ser. No. 10 / 893,804 entitled Delay Stage-Interweaved Analog DLL / PLL filed Jul. 19, 2004.BACKGROUND

[0002] 1. Field of the Disclosure

[0003] The present disclosure generally relates to memory systems and, more particularly, to an analog delay locked loop (DLL) or phase locked loop (PLL) with delay stage interweaving.

[0004] 2. Brief Description of Related Art

[0005] Most digital logic implemented on integrated circuits is clocked synchronous sequential logic. In electronic devices such as synchronous dynamic random access memory circuits (SDRAMs), microprocessors, digital signal processors, etc., the processing, storage, and retrieval of information is coordinated or synchronized with a clock signal. The speed and stability of the clock signal determines to a large extent the data rate at which a circuit can function. Many high speed integrated circuit devices, such as SDRAMs, micropro...

Examples

Embodiment Construction

[0038] Reference will now be made in detail to certain embodiments of the present disclosure, examples of which are illustrated in the accompanying figures. It is to be understood that the figures and descriptions of the present disclosure included herein illustrate and describe elements that are of particular relevance to the present disclosure, while eliminating, for the sake of clarity, other elements found in typical data storage or memory systems. It is noted at the outset that the terms “connected”, “connecting,”“electrically connected,” etc., are used interchangeably herein to generally refer to the condition of being electrically connected. It is further noted that various block diagrams, circuit diagrams and timing waveforms shown and discussed herein employ logic circuits that implement positive logic, i.e., a high value on a signal is treated as a logic “1” whereas a low value is treated as a logic “0.” However, any of the circuit discussed herein may be easily implemente...