Delay stage-interweaved analog DLL/PLL

Abstract

A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a divisional of U.S. application Ser. No. 10 / 893,804 entitled Delay Stage-Interweaved Analog DLL / PLL filed Jul. 19, 2004.BACKGROUND [0002] 1. Field of the Disclosure [0003] The present disclosure generally relates to memory systems and, more particularly, to an analog delay locked loop (DLL) or phase locked loop (PLL) with delay stage interweaving. [0004] 2. Brief Description of Related Art [0005] Most digital logic implemented on integrated circuits is clocked synchronous sequential logic. In electronic devices such as synchronous dynamic random access memory circuits (SDRAMs), microprocessors, digital signal processors, etc., the processing, storage, and retrieval of information is coordinated or synchronized with a clock signal. The speed and stability of the clock signal determines to a large extent the data rate at which a circuit can function. Many high speed integrated circuit devices, such as SDRAMs, micropro...

AI Technical Summary

Benefits of technology

The present invention relates to a synchronous circuit that includes a voltage-controlled delay line (VCDL) with multiple delay stages. The inventors have discovered that the prior art analog delay locked loop (ADLL) has limitations in terms of frequency range, locking time, and current consumption due to the usage of all delay stages for all frequencies of operation. The present invention proposes an approach to program the delay stages in the VCDL based on the operating condition, such as the frequency of the reference clock. This results in optimized delay stages that allow for broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. The deactivation or turning off of unused delay stages may conserve power at higher frequencies. The high frequency range of operation may be increased because of the removal of the prior art restriction of using a fixed number of delay stages for all input clock frequencies.

Problems solved by technology

At high reference clock frequencies, it may not be preferable to increase the number of VCDL stages because that may also increase the corresponding overall delay.

However, on the other hand, if less than optimum number of VCDL stages are employed, the VCDL may not properly function at low input clock frequencies.

However, with the same number (4) of VCDL stages, it may not be possible to obtain a delay range of 1 ns-4 ns which may be needed to accommodate a higher reference clock frequency (e.g., a frequency having a clock period tCK=1 ns).

The inventors have recognized that the frequency range of operation, locking time, and current consumption (e.g., at higher frequencies) of a prior art analog delay locked loop may be negatively affected because of the usage of all delay line stages for all frequencies of operation.

This arrangement not only consumes extra current (and, hence, power) at higher frequencies of operation, but also results in inefficient and inflexible usage of the delay line.

The usage of the entire delay line for each frequency delay operation results in slower locking time and a narrow frequency range of operation.

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