3-D rendering texture caching scheme

a 3d rendering and texture technology, applied in the field of computer graphics processors, can solve the problems of limited texel-to-pixel ratio for interpolation filtering (bilinear, trilinear, etc.), and achieve the effect of increasing the effectiveness of local texel reus

Inactive Publication Date: 2006-07-27
MANTOR MICHAEL +5
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0010] The present invention is a unique texture caching scheme for a three-dimensional rendering system that capitalizes on a span or area based polygon rasterization strategy with texture data spatially stored in memory to create a scenario where successive pixels will use and reuse neighboring texels significantly. In addition, when prefiltered texture mapping is used, as described in U.S. Pat. No. 4,727,365 to Bunker et al., the texel to pixel ratio will be limited for any interpolation filtering (bilinear, trilinear, etc.). This will cause overlapping samples to be reused more, and thus, it will increase the effectiveness of local texel reuse when employing the texture caching scheme of the present invention.
[0011] When processing successive pixels that are spatially related, the pixels will map to the same or neighboring texels, enabling the inventive texture caching scheme to store the least recently used cache lines to eliminate a significant number of external memory read data operations.
[0012] This new caching scheme will texture map at a minimum, one pixel per dock at peak rates and can make use of inexpensive external main memory devices. The mechanism efficiently pre-fetches data at the memory access granularity from main memory and stores it in cache memory. The organization of the cache is such that it achieves a very large reuse of texels with a minimum of cache memory. The novel caching technique of the present invention achieves good caching coherency, minimizes cache misses and utilizes inexpensive memory to achieve high speed polygon texturing.

Problems solved by technology

In addition, when prefiltered texture mapping is used, as described in U.S. Pat. No. 4,727,365 to Bunker et al., the texel to pixel ratio will be limited for any interpolation filtering (bilinear, trilinear, etc.).

Method used

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Embodiment Construction

[0041]FIG. 1 illustrates a functional block diagram of a computer display system. This system generally includes a Central Processing Unit (CPU) 12, a bridge chipset 14, a main memory 24, input devices 22, a display 18, a local graphics memory 20, and a Computer Graphic Processor (CGP) 16. The CGP 16 determines the graphical information to be sent to the display 18 based on inputs from the CPU (12) and data in main memory (24) and local graphics memory (20). The CPU (12) has access to data stored on disk, networks, or CD-ROM, etc. and based on power on sequences, programs booted at start up, and user inputs by the input devices, the CPU (12) will determine the data stream sent to the CGP (16). This data stream will be used by the CGP (16) to create the desired image on the display (18). The viewer is linked to the computer image generation process through an input control device (22) such as a keyboard, mouse, joystick, etc.

[0042] The CGP (16) described in this invention is large a...

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Abstract

A 3D rendering texture caching scheme that minimizes external bandwidth requirements for texture and increases the rate at which textured pixels are available. The texture caching scheme efficiently pre-fetches data at the main memory access granularity and stores it in cache memory. The data in the main memory and texture cache memory is organized in a manner to achieve large reuse of texels with a minimum of cache memory to minimize cache misses. The texture main memory stores a two dimensional array of texels, each texel having an address and one of N identifiers. The texture cache memory has addresses partitioned into N banks, each bank containing texels transferred from the main memory that have the corresponding identifier. A cache controller determines which texels need to be transferred from the texture main memory to the texture cache memory and which texels are currently in the cache using a least most recently used algorithm. By labeling the texture map blocks (double quad words), a partitioning scheme is developed which allow the cache controller structure to be very modular and easily realized. The texture cache arbiter is used for scheduling and controlling the actual transfer of texels from the texture main memory into the texture cache memory and controlling the outputting of texels for each pixel to an interpolating filter from the cache memory.

Description

[0001] This application is a continuation of U.S. Ser. No. 09 / 502,994, filed on Feb. 11, 2000, entitled “3-D Rendering Texture Caching Scheme”, which is a non-provisional utility application of U.S. Provisional Application No. 60 / 119,681 filed on Feb. 11, 1999.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention generally relates to a Computer Graphics Processor (CGP) that has 3D rendering and texturing capabilities and more particularly, to improvements in the method of rendering with application of texture data. The invention will minimize the necessary external bandwidth requirements for texture data and increase the rate at which texture data is available for use in the CGP. The invention also includes an apparatus for an implementation of the methods described herein. [0004] 2. Description of the Prior Art [0005] A CGP is commonly used for displaying images on a display screen that can be comprised of two dimensional data and / or three dimens...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G09G5/00
CPCG06T1/60G06T15/04G09G3/003G09G5/39G09G2360/121
Inventor MANTOR, MICHAELCAREY, JOHN AUSTINTAYLOR, RALPH CLAYTONPIAZZA, THOMAS A.POTTER, JEFFREY D.SOCARRAS, ANGEL E.
Owner MANTOR MICHAEL
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