Analog-to-digital converter

Abstract

An analog to digital converter circuit includes an isolation circuit, an input circuit including a resistor chain, a plurality of fixed threshold comparators, and an encoder. The resistor chain includes a plurality of resistors connected in series, the isolation circuit being configured to isolate a device supplying the analog input signal from the input circuit. The isolation circuit is connected to the input circuit at a top node of the resistor chain, and wherein 2N values of the analog input voltage are connected to inputs of the fixed threshold comparators to produce corresponding output signals. Methods of converting an analog signal to a digital signal are also described.

Description

TECHNICAL FIELD [0001] Aspects of the invention generally relate to analog-to-digital converter apparatuses and methods for converting analog signals to digital signals. More specifically, aspects of the invention relate to flash A / D converter apparatuses and methods. BACKGROUND OF THE INVENTION [0002] Analog-to-digital converters are necessary to take the “real” analog world into the digital world. Real world responses are typically not always linear. Most often, the response signal may have to be manipulated before it can be utilized. A common manipulation technique for such manipulation is compression. Compression is an important type of signal processing and is used not only to increase the dynamic range but also linearize many exponential-like functions. [0003] Compression increases the dynamic range of signals and if followed by decompression (e.g., companding) can raise the signal-to-noise (SNR) ratio. Compression can be performed in the analog domain using log amplifiers, as...

AI Technical Summary

Benefits of technology

[0014] In another aspect, a flash analog to digital converter circuit includes an input buffer configured as a common drain amplifier biased with a current, a resistive ladder having a plurality of resistors, a plurality of fixed threshold comparators, and an encoder. The input buffer is configured to isolate the resistive ladder from an analog input signal. The input buffer is connected to the resistive ladder at an uppermost node of the resistive ladder, and wherein 2N values of the an

Problems solved by technology

Logarithmic amplifiers are typically monolithic devices that have high power consumption (e.g., 25 mW) and DSP logic is intensive, leading to a large part count and excessive power dissipation.

These devices are therefore not desirable for some applications, particularly silicon-on-chip (SoC) technologies.

However, like most analog processors, these having high power consumption and are difficult to integrate on a chip.

There are, however, problems associated with this approach.

DSP also consumes high dynamic power and is mathematically intensive, leading to complex programming and lengthy application development cycles.

Analog preprocessing tends to dissipate large amounts of power, uses a large die area, and can be difficult to execute in CMOS technology, for example, due to non-linearities resulting from process variations.

ADC is typically power-intensive and bandwidth limiting.

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