Method for forming patterns and thin film transistors

a thin film transistor and pattern technology, applied in the field of pattern formation, can solve the problems of poor adhesion between the film and the substrate, thermal expansion coefficient, and substrate warpage, and achieve the effect of reducing the stress of the film efficiently and improving the yield rate of the thin film transistor

Inactive Publication Date: 2007-05-10
CHUNGHWA PICTURE TUBES LTD
View PDF3 Cites 7 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0026] The invention utilizes the method for forming a pattern of a discontinuous film, to avoid the substrate from being warped due to the uneven stress. The invention can reduce the stress of the films efficiently under the condition of a large-sized film. Besides, the method for forming a pattern of the present invention can be applied to the fabrication process of the thin film transistor in order to improve the yield rate of the thin film transistor.

Problems solved by technology

Especially, the uneven stress would occur between different layers, which have the large difference in thermal expansion coefficient, after a high temperature process, and therefore the substrate is severely warped.
It means that the adhesion between the film and the substrate, or between different films is poor, such that the film would peel.
Besides, during the photolithography process, the misalignment and exposure shifting would occur due to the warped substrate.
However, the problem caused by the uneven stress between the films becomes more and more serious with the increased size of the film, and therefore the development of the large-sized LCD TV would be limited.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for forming patterns and thin film transistors
  • Method for forming patterns and thin film transistors
  • Method for forming patterns and thin film transistors

Examples

Experimental program
Comparison scheme
Effect test

first embodiment

[0038]FIGS. 1A to 1C are schematic, cross-sectional diagrams illustrating the process flow for forming a pattern according to a preferred embodiment of the present invention. First, please refer to FIG. 1A, a substrate 100 is provided. Next, please refer to FIG. 1B, a discontinuous film 110 is formed on the substrate 100 to reduce the stress of the film 110. Finally, please refer to FIG. 1C, the discontinuous film 110 is patterned to form a pattern 120.

[0039] In an embodiment of the present invention, the method for forming the discontinuous film 110 on the substrate 100 as shown in FIG. 1B comprises a step of performing a deposition process 140 (shown in FIG. 2) by using a shadow mask 130. The deposition process 140 can be a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process.

[0040]FIG. 2 is a schematic side view showing that a deposition process is performed by using a shadow mask according to a preferred embodiment of the present invention. Plea...

second embodiment

[0047] The method for forming a pattern of the first embodiment can be applied to the fabrication process of a thin film transistor of the second embodiment. The thin film transistor can be a low temperature poly silicon thin film transistor (LTPS TFT) for example. FIGS. 6A to 6G are schematic, cross-sectional diagrams illustrating the process flow for making a thin film transistor according to a preferred embodiment of the present invention.

[0048] First, please refer to FIG. 6A, a substrate 300 is provided. The substrate 300 can be a glass substrate, a silicon substrate or a flexible substrate for example.

[0049] Next, a poly silicon island 340 is formed on the substrate 300 (as shown in FIG. 6D). In an embodiment of the present invention, the method of forming the poly silicon island 340 is shown in FIGS. 6B to 6D for example. Please refer to FIG. 6B, an amorphous silicon layer 320 is formed on the substrate 300 while the amorphous silicon layer 320 is a discontinuous film. Next,...

third embodiment

[0060]FIGS. 9A to 9E are schematic, cross-sectional diagrams illustrating the process flow for forming a thin film transistor according to another embodiment of the present invention.

[0061] First, please refer to FIG. 9A, a gate 510 is formed on a substrate 500. Next, please refer to FIG. 9B, a gate insulating layer 520 is formed on the substrate 500 to cover the gate 510. After that, please refer to FIG. 9C, a channel layer 530 is formed on the gate insulating layer 520 and the gate 510. Thereafter, please refer to FIG. 9D, a source / drain 550 is formed on the channel layer 530. At least one of the gate 510, the channel layer 530 and the source / drain 550 is formed by using the method for forming a pattern disclosed in the first embodiment.

[0062] Next, please refer to FIG. 9C, in an embodiment of the present invention, before the source / drain 550 is formed, the method further comprises a step of forming an ohmic contact layer 540 on the channel layer 530 for example. The ohmic cont...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

PropertyMeasurementUnit
stressaaaaaaaaaa
insulatingaaaaaaaaaa
thermal expansion coefficientaaaaaaaaaa
Login to view more

Abstract

A method for forming a pattern is provided. First, a substrate is provided. Then, a discontinuous film is formed on the substrate so as to reduce the stress of the film. After that, the discontinuous film is patterned to form a pattern. Besides, a method for manufacturing a thin film transistor (TFT) is also provided. First, a substrate is provided. Then, a poly silicon island is formed on the substrate. After that, a gate insulating layer is formed to cover the poly silicon island. Then, a gate is formed on the gate insulating layer. After that, a source/drain is formed in the poly silicon island below one side and the other side of the gate respectively, and a channel layer is formed between the source/drain. At least one of the poly silicon island and the gate is formed according to the above mentioned method for forming the pattern.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention generally relates to a method for forming a pattern. More particularly, the present invention relates to a method for forming a pattern capable of reducing the stress of a film, and a method for forming a thin film transistor using said method. [0003] 2. Description of Related Art [0004] The display apparatus is the communication interface between user and information media. Currently, the flat panel display is the trend in development. The flat panel display mainly includes organic electro-luminescence display (OELD), plasma display panel (PDP), thin film transistor liquid-crystal display (TFT-LCD) and so on. The TFT-LCD is in widespread use. [0005] The TFT-LCD is composed of a thin film transistor (TFT) array substrate, a color filter (CF) array substrate and a liquid crystal (LC) layer. The TFT array substrate comprises a plurality of pixel units arranged in an array. Each pixel unit is comp...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Applications(United States)
IPC IPC(8): H01L21/302
CPCH01L21/28506H01L21/31144H01L21/32051H01L21/76801H01L21/76802H01L21/76838H01L27/1214H01L29/66757H01L27/1288
Inventor CHENG, HSI-MING
Owner CHUNGHWA PICTURE TUBES LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap