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Semiconductor device and method of manufacturing the same

a technology of semiconductor devices and capacitors, applied in semiconductor devices, capacitors, electrical devices, etc., can solve the problems of reducing the yield of feram devices, achieve the effects of preventing the peeling off of the capacitor lower electrode, preventing the oxidation of the first and second conductive plugs, and improving the adhesion between the oxygen-barrier metal layer and the first insulating layer

Inactive Publication Date: 2007-05-24
FUJITSU LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention provides a semiconductor device and a method of manufacturing the same that can form a conductive plug connected to a capacitor and prevent abnormal oxidation of the conductive plugs. The method includes forming a first insulating layer over a semiconductor substrate, forming first and second holes in the insulating layer, and forming first and second conductive plugs in the first and second holes, respectively. An oxygen-barrier metal layer is then formed on the first conductive plug and an oxidation-preventing insulating layer is formed over the second conductive plug. A second insulating layer is then formed to cover the capacitor and the oxidation-preventing insulating layer. A third conductive plug is then formed in the second insulating layer to connect the second and third conductive plugs. The method prevents abnormal oxidation of the conductive plugs and avoids degradation of the dielectric layer.

Problems solved by technology

Also, oxidation of the tungsten plug spreads throughout the plug once such oxidation occurs, so that the contact failure is caused easily and reduction in the yield of the FeRAM device is brought about.

Method used

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  • Semiconductor device and method of manufacturing the same
  • Semiconductor device and method of manufacturing the same
  • Semiconductor device and method of manufacturing the same

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Experimental program
Comparison scheme
Effect test

first embodiment

[0068]FIGS. 2A to 2O are sectional views showing steps of manufacturing a semiconductor device according to a first embodiment of the present invention.

[0069] Next, steps required until a sectional structure shown in FIG. 2A is formed will be explained hereunder.

[0070] First, an element isolation recess is formed around a transistor forming region of an n-type or p-type silicon (semiconductor) substrate 1 by the photolithography method, and then an element isolation insulating layer 2 is formed by burying silicon oxide (SiO2) in the element isolation recess. The element isolation insulating layer 2 having such structure is called STI (Shallow Trench Isolation). In this case, an insulating layer formed by the LOCOS (Local Oxidation of Silicon) method may be employed as the element isolation insulating layer.

[0071] Then, a p-type well 1a is formed by introducing the p-type impurity selectively into the transistor forming region of the silicon substrate 1 in the memory cell region. ...

second embodiment

[0132] In the first embodiment, the iridium layer formed on the second and third conductive plugs 10b, 10c as the oxygen-barrier metal layer 11 and the iridium layer 14w formed as the lowermost layer portion of the lower electrode 14a of the capacitor Q are formed by separate steps.

[0133] Therefore, in the present embodiment, a structure in which one of two iridium layers is omitted will be explained hereunder.

[0134]FIGS. 3A to 3I are sectional views showing steps of manufacturing a semiconductor device according to a second embodiment of the present invention.

[0135] First, as shown in FIG. 3A, in compliance with the steps shown in the first embodiment, the MOS transistors T1, T2 are formed on the silicon substrate 1 and then the cover layer 7, the first interlayer insulating layer 8, and the first to third conductive plugs 10a to 10c are formed.

[0136] Then, as shown in FIG. 3B, the iridium layer is formed as a conductive oxygen-barrier metal layer 11a on the first to third cond...

third embodiment

[0166] In the lower electrodes 14a of the capacitors Q formed in accordance with the steps shown in the second embodiment, the peeling-off of the IrO layer 14x from the oxygen-barrier metal layer 11a rarely occurs.

[0167] Therefore, a structure for preventing the peeling-off of the IrO layer 14x from the oxygen-barrier metal layer 11a without fail in the multi-layered structure, which constitutes the lower electrodes 14a of the capacitors Q, and a method of forming the same will be explained hereunder.

[0168]FIGS. 4A to 4E are sectional views showing steps of manufacturing a semiconductor device according to a third embodiment of the present invention.

[0169] First, as shown in FIG. 4A, in compliance with the steps shown in the first embodiment, the MOS transistors T1, T2 are formed on the silicon substrate 1 and then the cover layer 7, the first interlayer insulating layer 8, and the first to third conductive plugs 10a to 10c are formed. Then, in compliance with the steps shown in ...

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Abstract

There are contained first and second conductive plugs formed in first insulating layer, an island-like oxygen-barrier metal layer for covering the first conductive plug, an oxidation-preventing insulating layer formed on the first insulating layer to cover side surfaces of the oxygen-barrier metal layer, a capacitor having a lower electrode formed on the oxygen-barrier metal layer and the oxidation-preventing insulating layer, a dielectric layer formed on the lower electrode, and an upper electrode formed on the dielectric layer, a second insulating layer for covering the capacitor and the oxidation-preventing insulating layer, a third hole formed in respective layers from the second insulating layer to the oxidation-preventing insulating layer on the second conductive plug, and a third conductive plug formed in the third hole and connected to the second conductive plug.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a divisional of application Ser. No. 10 / 388,596, filed Mar. 17, 2003, which is based on and claims priority to Japanese Patent Applications No. 2002-74566, filed on Mar. 18, 2002, No. 2002-249448, filed on Aug. 28, 2002, and No. 2003-64601, filed on Mar. 11, 2003, the contents of which are fully incorporated herein by reference.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, a semiconductor device having a capacitor and a method of manufacturing the same. [0004] 2. Description of the Prior Art [0005] The ferroelectric capacitor of FeRAM (Ferroelectric Random Access Memory) that is mass-produced currently has the planar structure. [0006] However, the capacitor having the stacked structure, a cell area of which can be reduced smaller, is needed in future in reply to the request for ...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L29/94H10B12/00H01L21/02H10B20/00H10B69/00
CPCH01L27/11502H01L28/55H01L27/11507H10B53/30H10B53/00H01L27/105
Inventor ANDO, TAKASHIMIURA, JIROHIROSAKA, YUKINOBUITOH, AKIOWATANABE, JUNICHISUEZAWA, KENKICHI
Owner FUJITSU LTD