High performance CMOS circuits, and methods for fabricating the same

Abstract

The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer, a metallic gate conductor, and a silicon-containing gate conductor. The second gate stack is located over a second device region (e.g., a p-FET device region) in the semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. The first and second gate stacks can be formed over the semiconductor substrate in an integrated manner by various methods of the present invention.

Description

FIELD OF THE INVENTION [0001] The present invention generally relates to semiconductor devices, such as high performance complementary metal-oxide-semiconductor (CMOS) circuits, that each contains at least one n-channel field effect transistor (n-FET) and at least one p-channel field effect transistor (p-FET). More specifically, the present invention relates to CMOS circuits that each contains at least one n-FET gate stack having a gate dielectric layer and a metallic gate conductor, and at least one p-FET gate stack having a gate dielectric layer and a silicon-containing gate conductor, as well as to methods for forming such CMOS circuits. BACKGROUND OF THE INVENTION [0002] In standard CMOS technology, an n-FET device uses an As (or other donor) doped n-type polysilicon layer as a gate electrode, which is deposited on top of a semiconductor oxide or semiconductor oxynitride gate dielectric layer. The gate voltage is applied through this n-doped polysilicon layer to create an invers...

AI Technical Summary

Benefits of technology

[0015] The first and second gate stacks as described hereinabove constitute a basic heterogeneous gate configuration for the semiconductor device of the present invention. Such first and second gate stacks may comprise one or more additional layers for further improvements of the device performance or manufacturability in the present invention.

[0047] oxidizing an exposed upper surface of the semiconductor substrate in the second device region to form a second gate dielectric layer, wherein the conductive oxygen diffusion barrier layer protects the first device region from oxidation;

[0052] oxidizing an exposed upper surface of the semiconductor substrate in the second device region to form a second gate dielectric layer, wherein the insulating oxygen diffusion barrier layer protects the first device region from oxidation;

Problems solved by technology

However, limitations of polysilicon gate electrodes are inhibiting further gains in the CMOS device performance.

However, integration of the metallic gate electrodes into the CMOS circuits has proven challenging.

Patterning, thermal budget restraints, and material interactions associated with front-end-of-line (FEOL) logic integration have been problematic for a number of candidate metal materials.

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