Semiconductor wafer, semiconductor device, and method of manufacturing semiconductor device

Abstract

Disclosed are a semiconductor wafer, a semiconductor device, and a method of manufacturing the semiconductor device, which are capable of easily carrying out an alignment between a semiconductor substrate and an electron beam exposure apparatus. There is provided a method including steps of: forming an interlayer insulating film 25 on a gate electrode 17a and a conductive film 17, as well as in a first opening 17b; forming in the interlayer insulating film 25 a second opening 25a including the first opening 17b; forming a hole 14a in an element isolation insulating film 14 under the first opening 17b; by use of the first opening 17b and the hole 14a as an alignment mark 27 used for the alignment in a state where a resist 28 is applied, measuring an intensity of a reflected electron EBref from the alignment mark 27, thus aligning the electron beam exposure apparatus with the semiconductor substrate 10; exposing with an electron beam EB the resist 28 existing in a hole formation region of a first region I; and developing the resist 28 to make a resist pattern 28e.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a divisional of application Ser. No. 11 / 061,469 filed Feb. 2, 2005, which is based on and claims priority of Japanese Patent Application No. 2004-332345 filed on Nov. 16, 2004, the entire contents of which are incorporated herein by reference.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a semiconductor wafer, a semiconductor device, and a method of manufacturing the semiconductor device. [0004] 2. Description of the Related Art [0005] In order to manufacture a semiconductor device such as LSI, an exposure process for exposing photo resist is needed, but among many methods, an electron beam exposure which uses an electron beam is extremely effective for attaining the refining of semiconductor devices, because it has a high resolution characteristic. [0006] However, in order to fully bring out such a high resolution characteristic, it is necessary to carry out the...

AI Technical Summary

Benefits of technology

[0019] According to the present invention, prior to exposing the resist with the electron beam, the alignment between the electron beam exposure apparatus and the semiconductor substrate is carried out by using the hole of the element isolating insulation film and the first opening of the conductive film as the alignment mark and by scanning this mark with the electron beam to measure the intensity of the reflected electron. Because this mark is constituted by not only the first opening of the conductive film but the hole of the element isolating insulation film thereunder, the depth of the mark becomes deeper than the case where only the first opening is used as the mark. Since the intensity of the reflected electron varies largely due to such a deep mark when the mark is scanned with the electron beam, the position of the mark can easily be determined in the present invention, and even if the underlying layer of the resist is a thin conductive film for gate electrode, the alignment between the semiconductor substrate and the electron beam exposure apparatus can be carried out with high precision.

[0022] Alternatively, the chip region of a semiconductor substrate may be employed as the second region, and the region included in this chip region may be employed as the first region. If doing this way, the distance between each point inside the chip region and the first region will be shorter as compared with the case where the first region is present outside the chip region. The positional misalignment of the chip region can be therefore corrected with higher precision by scanning the mark formed in the first region with the electron beam.

Problems solved by technology

However, in the case where a film for devices, such as a conductive film for gate electrodes, is formed on the semiconductor substrate 1, the recess which is formed under this conductive film and which an electron beam does not reach cannot be used as the alignment mark.

For this reason, as shown in the lower view of FIG. 2, because the S / N ratio of the graph 9 which indicates the intensity of the reflected electron becomes smaller, it is difficult to determine where the opening 3a exists, and thereby the alignment between the semiconductor substrate 1 and the electron beam exposure apparatus will be difficult.

However, the formation of such a conductive film 3 having a thick thickness makes it impossible to form refined gate electrodes.

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