Self-aligned complementary ldmos

a complementary, self-aligning technology, applied in the direction of semiconductor devices, electrical equipment, transistors, etc., can solve the problem of increasing rdson

Inactive Publication Date: 2007-10-04
SEMICON COMPONENTS IND LLC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Benefits of technology

[0006]In one form, the invention comprises a self-aligned LDMOS device having a gate situated on a high voltage well, the gate having a gate oxide on the high voltage well and a polysilicon layer on the gate oxide, a source region in the high voltage well on a source side of said gate, a drain region in the high voltage well on a drain side of said gate, and wherein the gate oxide is thick on the drain side of said gate.
[0007]An embodiment of the invention is a method of forming a self-aligned LDMOS device by providing a high voltage well with an

Problems solved by technology

Such a drift region, however, increases the Rdson, which in conventiona

Method used

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Embodiment Construction

[0047]Referring to FIG. 1, there is shown an n-type embodiment 50 of a fully self-aligned complementary LDMOS device according to one embodiment of the present invention. As shown in FIG. 1 the LDMOS device 50 is a multiple gate device. The LNDMOS 50 includes a source 52, three gates 54, 56, and 58 each having a thick gate oxide 60, and a drain 62. The gate 56 is between the source 52 and the drain 62, while the gate 54 is on the opposite side of the source 52, and the gate 58 is on the opposite side of the drain 62. The source 52 and drain 62 are formed in a high voltage HV NWELL 64. Under the HV NWELL 64 may be another layer 66 which may be an N buried layer or an N isolation layer, built in a P type substrate, depending on the use of the LDMOS 50, such as whether the LDMOS 50 is integrated in a low voltage CMOS platform and if the LDMOS 50 is subjected to relatively high voltages from the source and drain to the substrate compared to lower voltage devices or LDMOS device 50 with ...

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Abstract

The invention includes a laterally double-diffused metal-oxide semiconductor (LDMOS) having a reduced size, a high breakdown voltage, and a low on-state resistance. This is achieved by providing a thick gate oxide on the drain side of the device, which reduces electric field crowding in the off-state to reduce the breakdown voltage and forms an accumulation layer in the drift region to reduce the device resistance in the on-state. A version of the device includes a low threshold voltage version with a thin gate oxide on the source side of the device and a high threshold voltage version of the device includes a thick gate oxide on the source side. The LDMOS may be configured in an LNDMOS having an N type source or an LPDMOS having a P type source. The source of the device is fully aligned under the oxide spacer adjacent the gate to provide a large SOA, to reduce the device size and to reduce the device leakage.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]This application claims the benefit of provisional application Ser. No. 60 / 788,874 filed on Apr. 3, 2006, and is incorporated herein by reference.FIELD OF THE INVENTION[0002]This invention relates to semiconductor devices, and more specifically to LDMOS devices.BACKGROUND OF THE INVENTION[0003]In MOS power devices, such as a lateral double-diffusion metal-oxide semiconductor (LDMOS) device, there is generally a tradeoff between three factors: breakdown voltage (BVdss), on-state resistance (Rdson), and safe operating area (SOA), wherein BVdss and Rdson have a conflicting relationship (e.g., an increase in BVdss results in a higher Rdson), BVdss and SOA aid each other (e.g., an increase in BVdss results in a larger SOA), and Rdson and SOA may have a conflicting or aiding relationship. The BVdss may be increased by spacing the drain region from the gate, thus forming a drift region. Such a drift region, however, increases the Rdson, which in...

Claims

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Application Information

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IPC IPC(8): H01L29/76
CPCH01L21/823807H01L21/823814H01L21/823857H01L27/092H01L29/0869H01L29/66689H01L29/1083H01L29/1087H01L29/42364H01L29/42368H01L29/456H01L29/0878H01L29/7816
Inventor CAI, JUN
Owner SEMICON COMPONENTS IND LLC
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