Enhanced mobility MOSFET devices

Abstract

Semiconductor devices having enhanced mobility regions and methods of forming such devices are disclosed. In some embodiments, a method includes providing a SiGe layer on a supporting substrate, and forming isolation structures within the SiGe layer that define a first region and a second region. The conductivity of the SiGe layer in the second region may be altered to form a suitably doped well. A layer of strained Ge can be formed on the well, and a layer of strained Si may be formed on the surface of the first region. A layer of strained Si may be formed on the strained Ge layer. Source / drain regions may be formed in the well and in the first device region, and a dielectric layer may be formed on the Si layer. Gate structures may then be positioned on the dielectric layer.

Description

TECHNICAL FIELD[0001]The information disclosed herein relates generally to integrated circuit devices and fabrication methods, including semiconductor devices having enhanced mobility regions and methods of forming such devices.BACKGROUND[0002]The incorporation of increasing numbers of MOS transistor devices into progressively smaller integrated circuits remains an important challenge in Very Large Scale Integration (VLSI). For example, the implementation of complementary metal-oxide semiconductor (CMOS) logic typically includes a plurality of both p-channel metal-oxide semiconductor field-effect transistor (p-MOSFET) and n-MOSFET devices that constitute logic gates, which may be found in a variety of digital devices employed in computers, telecommunications and signal processing equipment. To date, aggressive dimensional reductions in the geometry of MOSFET devices have been achieved through the application of various scaling relationships to the MOSFET device. Briefly, and in gene...

AI Technical Summary

Benefits of technology

The patent text describes a method for improving the performance of semiconductor devices by using strained semiconductor materials. The method involves forming a semiconductor device with enhanced mobility regions using strained semiconductor materials. The strained materials can be formed by growing layers of silicon or silicon-germanium alloy on a relaxed layer of silicon. The method allows for the efficient and economical inclusion of p-MOSFET and n-MOSFET devices in a unitary structure. The technical effect of the method is improved performance and reduced size of semiconductor devices.

Problems solved by technology

The incorporation of increasing numbers of MOS transistor devices into progressively smaller integrated circuits remains an important challenge in Very Large Scale Integration (VLSI).

As the dimensions of MOSFET devices are reduced still further, however, other physical phenomena have become increasingly important in device behavior, which are not readily addressed by scaling.

High doping concentrations (in excess of about 3×1018 / cm3) have nevertheless adversely affected channel carrier mobility, as well as generally lowering the turn-on current for the device.

Although the foregoing strained semiconductor structures constitute improvements in the state of the art, the two approaches are not readily fabricated in a unitary structure, so that the fabrication of integrated devices having CMOS logic (which generally includes p-MOSFET and n-MOSFET devices) is not generally possible.

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